The workshop is organized at the Munich University of Applied Sciences. The building is the R building at Lothstraße 64 (map). You can reach it by subway, tram or buses from various directions.
You can identify the building by the “red cube” lecture hall beside its entrance. Once you enter the building you can find the workshop in the left part of the building on the third floor. It takes place in room R3.017.
Embedded UVM (or EUVM) is completely opensource and since it is natively compiled, it does not have any dependency on SystemVerilog or any other simulator. The source code of EUVM is available on Github in the repositories https://github.com/coverify/euvm and https://github.com/coverify/esdl. EUVM integrates seamlessly with Icarus Verilog and other simulators to enable an opensource UVM verification environment complete with constrained randomization. EUVM implements the latest IEEE UVM standard.
Some ready to compile EUVM powered Verilog testbenches are available on Github in the various repositories of http://github.com/uvm account.
The author of Verilator walks through 10 creative ways to use Verilator, from the “obvious” use as a simulator, finding possible simulation-synthesis mistakes, though using Verilator’s XML output to visualize design information.
You don’t have to write your testbench in C++ or Python just because you want to use Verilator. In this presentation we show you how to build and run modern testbenches with Verilator written in SystemVerilog even when Verilator doesn’t support classes.
Are you curious to know about what can be done with Open Source Silicon cores and tools? In this hands-on tutorial you will be working with some of the common key components in the open source silicon ecosystem such as CoCoTB, Verilator, FuseSoC and SweRV.
The workshop will take you from designing a simple peripheral controller, verifying it, connecting it to a RISC-V SoC and running system-level simulations.
If time permits, the same design will also be run on FPGA hardware.
