The CHIPS Alliance holds workshops in various locations throughout the year, based upon the needs of our project and members. Members of the CHIPS Alliance receive a number of complementary passes each year, based upon their membership level.
CHIPS Alliance Workshops and Meetings
» CHIPS Alliance Fall Workshop
Check out the schedule and register for free here:
8:00 a.m. PT – Welcome / Opening Remarks – Rob Mains, CHIPS Alliance
8:05 a.m. PT – Porting Android to RISC-V – Jing Yang, Alibaba
8:25 a.m. PT – Practical Adoption of Open Source System Verilog Tools – Michael Gielda, Antmicro: This talk will discuss the recent specific milestones achieved and tools created to support SystemVerilog development with open source tools. Things like automatic, CI-assisted linting and formatting as well as fully open source synthesis and simulation of a growing range of SystemVerilog designs such as SWeRV, BlackParrot etc. with Surelog/UHDM, as well as integration with open source ASIC design flows via OpenROAD/OpenLANE.
8:45 a.m. PT – Chisel Advances for Next-gen SoC Designs – Jack Koenig, SiFive: Chisel is a hardware construction language embedded in a general purpose programming language (Scala). It empowers hardware designers to use modern software engineering practices in the creation of hardware generators. The forthcoming Chisel v3.5.0 release includes many exciting features to further push the envelope of hardware design. These features include new APIs for hierarchical design, improved support for verification libraries, a new “view” primitive for mapping between types, better integration with non-hardware classes, Scala 2.13 support, and more.
9:05 a.m. PT – Open FASOC – Mehdi Saligane, University of Michigan (UMICH): OpenFASOC addresses the need for fully open source and automated analog IC generation. It is heavily based on FASOC, DARPA’s IDEA program and focuses on the open source SkyWater 130 nm PDK. The framework uses a cell-based approach to analog generation and relies on tools such as OpenROAD for push-button layout generation. This talk will go through a few of our open-source analog generators (temperature sensor, DLDO), our implemented designs in Google’s free shuttles MPW-I and II and blocks we would like to support in the future.
9:35 a.m. PT – FPGA Tooling Interoperability with the FPGA Interchange Format – Maciej Kurc, Antmicro: There has been a tremendous development in open source FPGA-oriented tooling in the recent years, with significant progress being made for Xilinx, Lattice, QuickLogic and other platforms. Most of those tools are however not interchangeable – they operate as separate complete netlist-to-implementation flows, mainly because they differ in data representation and formats they use for storage. The talk introduces the FPGA Interchange Format, a CHIPS project developed in collaboration between Google, Antmicro, Xilinx and others, that aims at removing the barrier by providing a common data representation and storage format for FPGA architecture, design netlist and cell placement and routing. With the introduction of a unified representation, different tools may be used together for greater flexibility. Moreover the FPGA interchange format lowers the barriers for new tools which can implement specific stages in isolation and plug in to existing flows.
9:55 a.m. PT – OmniXtend Milestone Updates – Dejan Vucinic, Western Digital Corporation
10:15 a.m. PT – Open Source NVME IP with AI Acceleration – Anand Kulkarni, Western Digital Corporation and Karol Gugala, Antmicro
10:35 a.m. PT – Automating Analog Layout using ALIGN – Sachin Sapatnekar, University of Minnesota (UMN): This talk overviews ALIGN, a joint university-industry effort that is developing an automated open-source flow for analog layout synthesis. ALIGN targets a variety of designs – low frequency analog circuits, wireline circuits for high-speed links, RF/wireless circuits and power delivery circuits – under a single framework. The flow is structured modularly and is being built to cater to a range of designer expertise: novice designers may use it in “push-button” mode, and expert users may bypass parts of the flow to incorporate their preferences and constraints.Register »Register »
» CHIPS Alliance Deep Dive Cafe Talks: Learning To Play the Game of Macro Placement with Deep Reinforcement Learning
Young-Joon Lee at Google will present a learning-based approach to macro placement, one of the most complex and time-consuming stages in the chip design process. Unlike prior methods, this approach has the ability to learn from past experiences and improve over time. Young-Joon Lee will discuss how his team posed macro placement as a Reinforcement Learning (RL) problem and trained an agent to place the cells of a netlist onto a floorplan area. The team also developed a novel edge-based graph convolutional neural network architecture capable of learning rich and transferable representations of the block. This method is capable of leveraging past experiences to become both better and faster at solving new instances of the problem. The objective is to minimize total wirelength under predefined congestion and density targets. Young-Joon Lee will show that for the floorplan blocks of modern accelerator chips, this method can generate high quality macro placements in terms of power, performance, and area in under six hours, whereas the baseline approach requires human experts on multiple iterations and takes several weeks.
Young-Joon Lee is a physical design engineer at Google Cloud. Before joining Google, Young-Joon received a PhD degree from Georgia Tech and worked at Intel Labs for six years. At Google, Young-Joon has been working on ML chip projects and ML-based physical design projects for two years. Young-Joon has experience in CAD/EDA algorithms, physical design, and machine learning, and aspires to use machine learning to accelerate chip design.Register »Register »
» CHIPS Alliance Deep Dive Cafe Talks: Advanced Interface Bus (AIB) Die-to-Die PHY Deep Dive
Date: Aug. 10, 2021
Experts on PHYs, protocols, EDA and heterogeneous integration gave talks on the latest developments on die-to-die interfacing. Read on for more information about this event with Intel and Blue Cheetah Analog Design, Inc.
AIB Deep Dive Kickoff with David Kehlet, Research Scientist, Intel
AXI Protocols for Die-to-Die Interoperability with Nij Dorairaj, Senior Engineer, Intel: Nij covered AXI protocol over AIB and how it enables end-to-end AXI interface across chiplets. He provided details on how AXI4-Streaming and AXI4 signals are mapped over AIB to achieve this with examples. Nij also discussed channel alignment usage with AXI and its necessity for multi-channel protocols.
Die-to-die Standards for 3D Heterogenous Integration with Dr. Farhana Sheikh, Senior Engineer, Intel: Farhana shared a high-level overview of need for die-to-die standards for 3D heterogeneous integration and a review of AIB-3D concept, along with the company’s plans for open sourcing an early AIB-3D specification in 2022.
AIB Chiplet Ecosystem with Martin Won, Senior Member of Technical Staff, Intel: Martin covered how AIB-based chiplets and the AIB-based chiplet ecosystem helps Intel achieve product goals and technology pathfinding to new areas of potential product development. He also discussed how Intel built the Stratix and Agilex families, including integration of the first non-Intel designed AIB-based chiplets into our FPGA products.
AIB and Chiplet Interface Generators with Krishna Settaluri, CEO, Blue Cheetah Analog Design: Krishna covered how Blue Cheetah’s generators enable rapid configurability of circuits for chiplet interfaces and highlighted the results / verified outputs of the AIB generator.
AIB on Standard Packaging, Lai Guan Tang with Principal Engineer, Intel: Lai Guan covered AIB scaling over different package technologies and the concept of using a common AIB PHY to scale to multiple bandwidth densities.
» CHIPS Alliance Deep Dive Cafe Talks: Verible/UHDM Presented by Google
SystemVerilog is one of the most used languages for hardware modelling. The available open source tooling does not universally support the whole feature set yet which can be a limitation for projects considering these tools. This talk covered the CHIPS Alliance’s efforts to provide strong support for SystemVerilog ranging from a compiler frontend using Surelog and UHDM for tools such as Yosys and Verilator to the formatting and linting tool Verible.
Henner Zeller is a software engineer who has been with Google for more than 15 years with a passion for open source and hardware. He had been responsible for the Google web crawler before shifting his focus to improve the open source ecosystem for hardware modelling.
» Dynamic Scheduling in Verilator Presented by Antmicro
Date: June 15, 2021
The presentation discussed the current status of the work towards UVM support in open source tooling. Karol discussed the current state of the ecosystem and the latest milestone – a dynamic stratified scheduler implementation in Verilator, which opens the door to running event-driven simulations in the popular open source HDL simulation framework.
Karol Gugala is an Engineering Manager at Antmicro, where he is working with open source in various contexts – primarily FPGA and embedded software. Open source enthusiast – involved in a wide variety of FOSS projects.
» Momentum in Open Source Hardware Projects
Date: June 9, 2021
This panel was hosted by the OpenPower Foundation and featured perspective on a variety of topics including open cores and open tooling. The session also covered recent projects in the open source ecosystem such as LibreBMC and the Open Source MPW Shuttle Program.
Panelists included: James Kulina, Executive Director, OpenPOWER Foundation; Rob Mains, General Manager, CHIPS Alliance; Tim Ansell, Software Engineer, Google; and Michael Gielda, VP Business Development, Antmicro.
» CHIPS Alliance Spring Workshop
Date: March 30, 2021
This live workshop discussed the latest updates in collaborative open source chip design, protocols, and tooling. Check out the slides below:
- Welcome / Opening Remarks: Rob Mains, CHIPS Alliance
- Chipyard: Bora Nikolic, UC Berkeley
- RISC-V DV Workgroup Updates: Tao Liu / Matt Cockrell, Google
- Open Source Flows in ASIC & FPGA Development: Michael Gielda, Antmicro
- Open-Source AIB Chiplet Ecosystem: David Kehlet, Intel
- OmniXtend Milestone Updates: Dejan Vucinic, Western Digital
- Chisel Advances for Next-gen SOC Designs: Henry Cook, SiFive
- Codasip SweRV Core Support Package in a Nutshell: Zdenek Prikyl, Codasip
- An Introduction to the OpenROAD Project: Andrew Kahng / Tom Spyrou, OpenROAD
- Open Source FPGA Tooling: Brian Faith, Quicklogic
- Fully Open Silicon Down to the Transistor: Tim Ansell, Google
» CHIPS Alliance Workshop
Date: September 17, 2020
CHIPS Alliance, the open source RTL hardware and software development tool organization, gathered to share milestones, progress, updates and more. Check out the videos from the sessions:
- Welcome – Ted Marena, Western Digital
- Open Design Verification – Tao Liu, Google
- Enabling Fully Open Source And Continuous Integration-Driven Flows in ASIC and FPGA Development – Michael Gielda, Antmicro
- The Emergence of the Open-Source AIB Chiplet Ecosystem – David Kehlet, Intel
- Chipyard: Design of Customized Open-Source RISC-V SoCs – Borivoje Nikolic, UC Berkeley
- SweRV and/or OmniXtend Milestones – Zvonimir Bandic, WDC
- Chisel & FIRRTL for next-generation SoC designs – Jack Koenig, SiFive
- Open ML Accelerator – Anoop Saha, Mentor
- Cloud Based Verification of RISC-V Processors – Dan Ganousis, Metrics
- OpenROAD Open RTL-to-GDS Update – Andrew Kahng, OpenRoad/UCSD, and Mohamed Kassem, Efabless
- Open Source FPGA Tooling, Our Journey from Resistance to Adoption – Brian Faith, QuickLogic
» Production Grade, Open RISC-V SweRV Core Solutions in CHIPS Alliance
Date: May 20, 2020
This online meeting features presenters who can explain how to implement the production grade, open RISC-V SweRV Core into your design.
- Intro to CHIPS Alliance & SweRV family overview – Zvonimir Bandic, BoD CHIPS Alliance (15 mins)
- SweRV EH2 /EL2 architecture – Robert Golla, Western Digital (20 mins)
- SWeRV and open source tooling ecosystem – Michael Gielda, Antmicro (20 mins)
- SSP, SweRV Support Package for commercial support – Codasip (15 mins)
- Simulator in Google Cloud for SSP – Metrics (15 mins)
» Cache Coherent Memory Fabric based on RISC-V
Date: April 16, 2020
With RISC-V being an open ISA, this has enabled many open system architectural capabilities. One of these is the cache coherent Tilelink bus. Based on Tilelink, an open cache coherent memory fabric call OmniXtend was developed. This online meetup will discuss the latest updates, support and next steps for this revolutionary architecture.
- Login & say hello to each other
- TileLink Introduction – Wesley Terpstra , SiFive
- OmniXtend Overview – Zvonimir Bandic, Western Digital
- Tofino Programmable Switch OmniXtend – Curt Beckmann, Intel
- Latest developments & next steps
- Remaining Q & A
» CCC2020, the third Chisel Community Conference, hosted by CHIPS Alliance
Date: January 29-30, 2020
Location: Milpitas, CA
On January 29th-30th, CHIPS Alliance hosted CCC2020, the 3rd Chisel Community Conference. The first day had a full day of presentations on Chisel topics, followed by a poster session. The second day January 30th had a Chisel working day with break out rooms. Chisel is a hardware-construction language, hosted in Scala, and is used in both academia and industry to generate RTL for digital hardware. This event further promoted the Chisel language, FIRRTL compiler, and associated software ecosystem. Working with CHIPS Alliance, this event brought together the community for multiple talks, tutorials, discussions and more.
» Workshop on Open Source Design Verification
Date: November 14-15, 2019
Location: Munich, Germany
The CHIPS Alliance organizes a two day workshop in co-operation with the Munich University of Applied Sciences. The workshop covers tools for open source design simulation and verification.
The workshop invites contributions from industry, academia and hobbyists, either as talk or tutorial. Proposals should cover open source design simulation and verification, for example in the following categories (but not limited to):
- Open source simulation tools
- Open source design verification tools
- Open source rapid prototyping tools and methodologies
- Open source libraries for design verification
- Open source standards and methodologies for design verification
- Industry case studies of usage and integration of the aforementioned
Most importantly, your submitted proposal should cover the open source aspect.
The workshop will start on November 14 at 13:00 CEST and end on November 15 at 17:00 CEST. Accepted presentations and tutorials will be published soon.
» Inaugural workshop
Date: June 19, 2019
Location: Google, Sunnyvale, CA
CHIPS Alliance held their inaugural workshop on June 19th. The workshop focused on open source hardware, software tools, RTL development and related topics. Presentations were made by member companies and attendees had a forum to propose RTL design and development ideas. Workshop attendees learned more about our organization and the RTL designs we will be developing.