The CHIPS Alliance holds workshops in various locations throughout the year, based upon the needs of our project and members. Members of the CHIPS Alliance receive a number of complementary passes each year, based upon their membership level.
CHIPS Alliance Workshops and Meetings
Upcoming events
» CHIPS Alliance Spring Workshop
Location: Virtual
Please join this live workshop to hear the latest on collaborative open source chip design, protocols, and tooling. We are excited to share with the community exciting development across different areas of chip design.
Schedule (PT UTC-8)
- 8:00 – Welcome / Opening Remarks
- 8:10 – RISC-V DV Workgroup Updates
- 8:25 – Android on RISC-V
- 8:40 – Open Source Flows in ASIC & FPGA Development
- 8:55 – Open-Source AIB Chiplet Ecosystem
- 9:10 – OmniXtend Milestone Updates
- 9:25 – Chisel advances for next-gen SOC Designs
- 9:40 – Codasip SweRV Core Support Package in a Nutshell
- 9:55 – An Introduction to the OpenROAD project
- 10:25 – Open Source FPGA Tooling
- 10:40 – Fully Open Silicon Down to the Transistor
- 11:10 – Analog tooling
To learn more and register for free, please visit: https://www.eventbrite.com/e/chips-alliance-spring-workshop-tickets-142138836085
Past events
» CHIPS Alliance Workshop
Date: September 17, 2020
Location: Virtual
CHIPS Alliance, the open source RTL hardware and software development tool organization, gathered to share milestones, progress, updates and more.
- Welcome – Ted Marena, Western Digital
- Open Design Verification – Tao Liu, Google
- Enabling Fully Open Source And Continuous Integration-Driven Flows in ASIC and FPGA Development – Michael Gielda, Antmicro
- The Emergence of the Open-Source AIB Chiplet Ecosystem – David Kehlet, Intel
- Chipyard: Design of Customized Open-Source RISC-V SoCs – Borivoje Nikolic, UC Berkeley
- SweRV and/or OmniXtend Milestones – Zvonimir Bandic, WDC
- Chisel & FIRRTL for next-generation SoC designs – Jack Koenig, SiFive
- Open ML Accelerator – Anoop Saha, Mentor
- Cloud Based Verification of RISC-V Processors – Dan Ganousis, Metrics
- OpenROAD Open RTL-to-GDS Update – Andrew Kahng, OpenRoad/UCSD, and Mohamed Kassem, Efabless
- Open Source FPGA Tooling, Our Journey from Resistance to Adoption – Brian Faith, QuickLogic
» Production grade, open RISC-V SweRV Core Solutions in CHIPS Alliance
Date: May 20, 2020
Location: Virtual
This online meeting features presenters who can explain how to implement the production grade, open RISC-V SweRV Core into your design.
- Intro to CHIPS Alliance & SweRV family overview – Zvonimir Bandic, BoD CHIPS Alliance (15 mins)
- SweRV EH2 /EL2 architecture – Robert Golla, Western Digital (20 mins)
- SWeRV and open source tooling ecosystem – Michael Gielda, Antmicro (20 mins)
- SSP, SweRV Support Package for commercial support – Codasip (15 mins)
- Simulator in Google Cloud for SSP – Metrics (15 mins)
» Cache Coherent Memory Fabric based on RISC-V
Date: April 16, 2020
Location: Virtual
With RISC-V being an open ISA, this has enabled many open system architectural capabilities. One of these is the cache coherent Tilelink bus. Based on Tilelink, an open cache coherent memory fabric call OmniXtend was developed. This online meetup will discuss the latest updates, support and next steps for this revolutionary architecture.
- Login & say hello to each other
- TileLink Introduction – Wesley Terpstra , SiFive
- OmniXtend Overview – Zvonimir Bandic, Western Digital
- Tofino Programmable Switch OmniXtend – Curt Beckmann, Intel
- Latest developments & next steps
- Remaining Q & A
» CCC2020, the third Chisel Community Conference, hosted by CHIPS Alliance
Date: January 29-30, 2020
Location: Milpitas, CA
On January 29th-30th, CHIPS Alliance hosted CCC2020, the 3rd Chisel Community Conference. The first day had a full day of presentations on Chisel topics, followed by a poster session. The second day January 30th had a Chisel working day with break out rooms. Chisel is a hardware-construction language, hosted in Scala, and is used in both academia and industry to generate RTL for digital hardware. This event further promoted the Chisel language, FIRRTL compiler, and associated software ecosystem. Working with CHIPS Alliance, this event brought together the community for multiple talks, tutorials, discussions and more.
» Workshop on Open Source Design Verification
Date: November 14-15, 2019
Location: Munich, Germany
The CHIPS Alliance organizes a two day workshop in co-operation with the Munich University of Applied Sciences. The workshop covers tools for open source design simulation and verification.
The workshop invites contributions from industry, academia and hobbyists, either as talk or tutorial. Proposals should cover open source design simulation and verification, for example in the following categories (but not limited to):
- Open source simulation tools
- Open source design verification tools
- Open source rapid prototyping tools and methodologies
- Open source libraries for design verification
- Open source standards and methodologies for design verification
- Industry case studies of usage and integration of the aforementioned
Most importantly, your submitted proposal should cover the open source aspect.
The workshop will start on November 14 at 13:00 CEST and end on November 15 at 17:00 CEST. Accepted presentations and tutorials will be published soon.
» Inaugural workshop
Date: June 19, 2019
Location: Google, Sunnyvale, CA
CHIPS Alliance held their inaugural workshop on June 19th. The workshop focused on open source hardware, software tools, RTL development and related topics. Presentations were made by member companies and attendees had a forum to propose RTL design and development ideas. Workshop attendees learned more about our organization and the RTL designs we will be developing.