The Chisel Workgroup is formed around the eponymous hardware design language (HDL) that facilitates advanced circuit generation and design reuse for both ASIC and FPGA digital logic designs. Chisel adds hardware construction primitives to the Scala programming language, providing designers with the power of a modern programming language to write complex, parameterizable circuit generators that produce synthesizable Verilog. Chisel is powered by FIRRTL (Flexible Intermediate Representation for RTL), a hardware compiler framework that performs optimizations of Chisel-generated circuits and supports custom user-defined circuit transformations on an Intermediate Representation. The WG also covers tools such as Treadle which is an experimental circuit simulator that executes the Firrtl IR.
