#project-update #openlane #openroad #yosys #surelog #uhdm #swerv #ibex #core-v #blackparrot #opemtitan #risc-v October 27, 2021 Improving the OpenLane ASIC Build Flow with Open Source SystemVerilog Support
#project-update #systemverilog #verible #yosys #verilator #uhdm #surelog July 20, 2021 Progress on Building Open Source Infrastructure for System Verilog
#announcement #openroad #yosys #f4pga May 20, 2021 Efabless Launches chipIgnite with SkyWater to Bring Chip Creation to the Masses
#project-update #fusesoc #swervolf #serv #verilator #symbiflow #openroad #yosys #risc-v February 23, 2021 Goings-on in the FuseSoC Project and Other Open Source Silicon Related News
#project-update #yosys #verilator #uhdm #surelog #ibex #risc-v #opentitan January 7, 2021 Enabling Open Source Ibex Synthesis and Simulation in Verilator/Yosys via UHDM/Surelog
#announcement #openroad #yosys #f4pga December 15, 2020 Efabless Joins CHIPS Alliance to Accelerate the Growth of the Open Source Chip Ecosystem
