#project-update #systemverilog #verible #yosys #verilator #uhdm #surelog July 20, 2021 Progress on Building Open Source Infrastructure for System Verilog
#project-update #systemverilog #verible #language-server-protocol #lsp #asic-design January 22, 2020 Intel joins CHIPS Alliance to promote Advanced Interface Bus (AIB) as an open standard
