#project-update #caliptra #veerJune 29, 2026Dual-core Lockstep in the VeeR EL2 RISC-V core for safety-critical applications and side-channel access mitigation in Caliptra RoT
#project-update #caliptra #veerMay 22, 2025Generating interactive coverage dashboards for VeeR and Caliptra with Coverview
#project-update #topwrap #fpgaDecember 20, 2024Topwrap – open source toolkit for modular, parameterizable digital logic design
#project-update #verilator #uvm #systemverilog #opemtitanJune 21, 2024Initial assertion control support in Verilator
#project-update #verilator #uvm #systemverilogNovember 8, 2023Initial Open Source Support for UVM Testbenches in Verilator
#project-update #verilatorSeptember 29, 2023Verilator Model Generation Performance Improvements and Initial Multithreaded Verilation Support
#project-update #systemverilog #uvm #verilatorJuly 21, 2023Progress in open source SystemVerilog / UVM support in Verilator
