Projects

CHIPS Alliance hosts many open source projects at various stages of their maturity lifecycle.

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Graduated Projects

FPGA tool perf

FPGA tool perf

Framework for automatic FPGA toolchains benchmarking

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OpenPRoT

OpenPRoT is a specification and an open-source implementation of a standards-based Platform Root of Trust firmware stack.

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Surelog and UHDM

SureLog is a SystemVerilog 2017 Pre-processor, Parser, UHDM Compiler providing IEEE Design/TB VPI and Python AST API. UHDM is the underlying Hardware Data Model framework. More info: https://woset-workshop.github.io/WOSET2020.html#article-10

VeeR

VeeR

RTL designs for the VeeR (Very Efficient & Elegant RISC-V) cores (EH1, EH2, EL2).

Caliptra

Caliptra

The Caliptra project focuses on development of HW and SW IP for the Caliptra Root of Trust

Chisel

Chisel

Support the Chisel Hardware Construction Language and related projects

F4PGA

F4PGA

Free and open source toolchain for FPGA devices

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FPGA Interchange format

FPGA Interchange is a Vendor agnostic FPGA devices and designs description. It enables interoperability between different FPGA tools.

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Intel Compiler for SystemC

Open source SystemC to SystemVerilog translation tool and SingleSource library.

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RocketChip

The SoC generator instantiates the RISC-V Rocket Core and relevant component.

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SV tools

SystemVerilog toolchain / suite for working with SV/UVM