Events

CHIPS Alliance at DAC 2025

CHIPS Alliance is pleased to participate in the 62nd Design Automation Conference (DAC), taking place June 22–25, 2025, at the Moscone Center West in San Francisco. DAC is a key industry gathering for the semiconductor and electronic design automation (EDA) community, with a growing focus on open source contributions to chip and system design. Don’t miss CHIPS Alliance Executive Director Rob Mains presenting:

Session: The Evolution of Collaborative Open Source Hardware Development Date/Time: Wednesday, June 25 | 10:30am – 12:00pm PDT Location: Room 2012, Level 2 Track: Engineering Special Session – Systems and Software

Rob will explore how open source silicon initiatives—such as Caliptra, Chisel, and collaborative firmware efforts—are transforming the way companies, universities, and individuals contribute to the development of secure and scalable hardware platforms. The session will highlight practical strategies for ecosystem collaboration, integration into design flows, and opportunities for new contributors.

We invite attendees to connect with CHIPS Alliance representatives during the conference to learn how to get involved in current projects and shape the future of open source hardware design.

Details here

CHIPS Alliance Spring Workshop 2021

Check out the presentations below, and watch the replay here

• Chipyard - Bora Nikolic, UC Berkeley (slides)
• RISC-V DV Workgroup Updates Tao Liu / Matt Cockrell, Google (slides)
• Open Source Flows in ASIC & FPGA Development Michael Gielda, Antmicro
• Open-Source AIB Chiplet Ecosystem David Kehlet, Intel (slides)
• OmniXtend Milestone Updates Dejan Vucinic, Western Digital (slides)
• Chisel advances for next-gen SOC Designs Jack Koenig, SiFive (slides)
• Codasip SweRV Core Support Package in a Nutshell Zdenek Prikyl, Codasip (slides)
• An Introduction to the OpenROAD project Andrew Kahng / Tom Spyrou, OpenROAD (slides)
• Open Source FPGA Tooling Brian Faith, Quicklogic (slides)
• Fully Open Silicon Down to the Transistor Tim Ansell, Google (slides)

Watch the Replay

CHIPS Alliance Fall Workshop 2021

Check out the presentations below, and watch the replay here

• Porting Android to RISC-V Alibaba – Guoyin Chen and Han Mao, Alibaba (replay) (slides)
• Practical Adoption of Open Source System Verilog Tools – Michael Gielda, Antmicro (replay) (slides)
• Chisel and FIRRTL for Next-Generation SoC Designs– Jack Koenig, SiFive (replay) (slides)
• OpenFASOC: Automated Open Source Analog and Mixed-Signals IC Generation – Mehdi Saligane, University of Michigan (UMICH) (replay) (slides)
• FPGA Tooling Interoperability with the FPGA Interchange Format – Maciej Kurc, Antmicro (replay) (slides)
• OmniXtend: Scalability and LPC – Jaco Hofmann, Western Digital Corporation (replay) (slides)
• Open Source NVME IP with AI Acceleration – Anand Kulkarni, Western Digital Corporation and Karol Gugala, Antmicro (replay) (slides)
• Automating Analog Layout using ALIGN – Sachin Sapatnekar, University of Minnesota (UMN) (replay) (slides)

Watch the Replay

CHIPS Alliance First 2022 Biannual Technology Update

Watch the Replay

Check out the presentations below:

• Introduction – Rob Mains, CHIPS Alliance
• Updates of Android on RISC-V – Han Mao, Alibaba (slides)
• Chisel and FIRRTL for Next-Generation SoC Designs– Jack Koenig, SiFive (slides)
• Introducting the F4PGA Workgroup– Michael Gielda, Karol Gugala, Antmicro (slides)
• Chiplet IP Protocol– Dave Kehlet, Intel (slides)
• NVMe Computational Storage Processor for Edge & Datacenter Applications, Anand Kulkarni, Wester Digital (slides)
• Towards Open Source Models of Cryogenic CMOS : Brian Hoskins and Pragya Shrestha, NIST (slides)
• Latest Statistics from Google’s No Cost Shuttle Program : Tim Ansell, Google : (slides)

Watch the Replay

CHIPS Alliance Fall Workshop 2022

Check out the presentations below, and watch the replay here

• Caliptra – Bryan Kelly, Microsoft
• SBOM and HBOM / Zephyr - Kate Stewart, Linux Foundation
• F4PGA tools in the classroom - Mike Wirthlin, Jeff Goeders, BYU (slides)
• Datasets for Machine Learning for Chip Design - Aman Arora, UT-Austin (slides)
• Open source SystemVerilog / UVM support and scaling for large designs in Verilator 5.0 and beyond, Michael Gielda, Antmicro (slides)
• Lowering barriers to chip design using OpenFASOC, AWG activities and tapeouts, Mehdi Saligane, University of Michigan (slides)
• Global Foundries Open PDK, Karthik Chandrasekaran, Global Foundries
• Caravel SOC Learnings, Mohammed Kassem, Efabless, (slides)
• Intel Compiler for SystemC, Mikhail Moiseev, Intel (slides)
• Renode co-simulation for Caravel, Peter Gielda, Antmicro (slides)

Watch the Replay

CHIPS Alliance Summer Workshop 2023

Check out the presentations below, and watch the replay here

• Caliptra & VeeR continuous integration ecosystem – Michael Gielda, Antmicro (slides)
• Caliptra: Validating firmware against multiple hardware models in CI - Kor Nielsen, Google
• OmniXtend: coherent scaleout over commodity fabrics - Jaco Hoffman, Westen Digital (slides)
• CHISEL 3 and Beyond - Jack Koenig, SiFive (slides)
• Single Source library for digital design and virtual prototyping - Mikhail Moiseev, Intel (slides)
• Building Confidence in Open IC Design using OpenFASOC - Mehdi Saligane, University of Michigan (slides)

Watch the Replay

CHIPS Alliance at the Open Compute Project Global Summit

Please join us at the Open Compute Project Global Summit to hear about the Caliptra Root of Trust collaborative project.

Be sure to come visit us at booth C37 hosted by the Linux Foundation at the event.

Details here

RISC-V Summit North America 2023

Please join us at the RISC-V North American Summit November 7 - 8

Be sure to come visit us at the CHIPS Alliance booth at the event.

Details here:

CHIPS Technology Update - November 2023

Check out the presentations below, and watch the replay here

• Project Open Se Cura – Kenny Vassigh, Bangfei Pan, Cindy Liu, Kai Yick, Google, Michael Gielda, Antmicro, Brian Murray, Verisilicon (slides)
• Caliptra Workgroup Update - Andres Lagar-Cavilla, Google (slides)
• Enabling UVM testbenches in Verilator - Michael Gielda, Karol Gugala, Antmicro (slides)
• FuseSOC: Package manager and build abstraction tool for FPGA/ASIC development - Olof Kindgren, Qamcom (slides)
• CHIPYard: An Open Source RISC-V Design Frameowrk - Sagar Karandikar, U.C. Berkeley (slides)

Watch the Replay

Google Summer of Code 2024

As in previous years, CHIPS Alliance returns as a mentor organization for Google Summer of Code 2024. Become a contributor and join us in our mission to push forward open source hardware, ASIC and FPGA design. Explore our list of project ideas and submit by April 2: https://github.com/chipsalliance/ideas/blob/main/gsoc-2024-ideas.md

Open Hardware and Software: Accelerating Beyond Moore’s Law and Enabling the Next Wave of Innovation

Check out the presentations below:

• Introductions - Rob Mains, Linux Foundation (slides)
• How can software developers help keep Moore’s law alive? - Michael Gielda, Antmicro (slides)
• HBOM talk - Kate Stewart, Linux Foundation (slides)
• Scaling hardware design: squeezing every bit of performance of the open source OpenROAD ASIC toolchain - Karol Gugula, Antmicro (slides)
• Accelerating EDA Flows in the AWS Cloud - David Pellerin, AWS (slides)
• An Introduction to RISC-V - Keith Graham, Codasip (slides)
• Accelerating the RISC-V Software Development Ecosystem - Jeffrey Osler-Mixon, Red Hat (slides)
• Caliptra open source Root of Trust - Caleb Whitehead, Microsoft (slides)
• Getting “Ware” You Need to Go – Managing Open Hardware with Software (Part 1) - Maximillian Schmidt & Lance Albertson, Oregon State University (slides)
• Getting “Ware” You Need to Go - AI Software on Open Hardware (Part 2) - Christopher Sullivan , Oregon State University (slides)

Open Hardware Mini-Summit

Check out the presentations below:

• Welcome / Opening Remarks / Accelerating Innovation with Open Hardware Design - Rob Mains - General Manager, CHIPS Alliance
• RISC-V: Getting Involved, Latest Advancements - Andrea Gallo - VP Technology, RISC-V
• Open Source Simulators for Pre-Silicon Validation of Safety-critical RISC-V System-on-chip - Daniel Mueller-Gritschneder, Johannes Geier - Professor, TU Wien
• Making VeeR EL2 Caliptra 2.0-ready: enhanced functionalities, verification and documentation - Karol Gugala - Engineering Manager, Antmicro
• Value and Opportunities in Open Source for Circuit Design - Christoph Sandner - Senior Principal Engineer, Infineon
• Open Source IC design for Automotive: Real World Experience - Rob Taylor - Chief Strategy Officer, ChipFlow

CHIPS Alliance at OCP EMEA Summit 2025

Heading to the Open Compute Project Foundation EMEA Summit, and looking to learn how open source silicon is accelerating chip design? Visit Rob Mains and Stefano Righi at booth A13. CHIPS Alliance is proud to participate as an open source partner of the event. We’re looking forward to insightful discussions, sharing successes and challenges in collaborative hardware and firmware development, and connecting with the open compute community.

Don’t miss the Caliptra session on April 30 at 09:50 (Level 1 – Liffey Hall 2).

Join Raghu Krishnamurthy, Bryan Kelly, Bharat Pillili, and Christopher Swenson for a technical overview of the Caliptra subsystem firmware stack, an open source Root of Trust solution for data center-class SoCs. The session will highlight integration efforts, subsystem components, and the roadmap for Caliptra 2.0.

CHIPS Alliance welcomes participation and collaboration amongst companies, universities, and individuals.

Connect with Rob Mains and Stefano Righi here to pre-arrange a meeting, or visit them at booth A13 to learn about the latest developments and how to get involved.

Details here