CHIPS Alliance 2020 Annual Report

CHIPS Alliance was founded in March 2019 to design high-quality, open source hardware register transfer level (RTL) and develop open source hardware and software design tools. By creating an open and collaborative environment, companies and organizations can develop innovative, cost effective hardware designs optimized for the requirements of today’s silicon devices and FPGAs.

CHIPS Alliance was incorporated by four organizations which wanted to make open source silicon a reality. Esperanto, Google, SiFive and Western Digital were the founding members. Now that one year has passed since the organization’s founding, it is fitting to look back at our progress so far. We are pleased to present this annual report detailing the many things we have accomplished collectively in this fast growing organization.

Comments and feedback are welcome at info@chipsalliance.org.

“The growth behind CHIPS Alliance has been incredible. We are laying the foundation for open source hardware development to become accessible to a wider number of companies, universities and individuals.”

Zvonimir Bandic, Governing Board Chair, CHIPS Alliance, and Senior Director, Western Digital

 

WHO WE ARE

CHIPS Alliance is a barrier free, open organization focused on developing open source hardware RTL and open source hardware and software development tools. The organization desires to lower the cost of chip development through collaboration, leveraging the diverse expertise and broad experience of its members. CHIPS Alliance encourages contributions and shared investments by providing vendor-neutral promotional events, documentation, tools and support for a variety of projects in our workgroups.

CURRENT WORKGROUPS

The following workgroups are part of CHIPS Alliance:

  • Interconnect
    • OmniXtend
    • AIB (Chiplets)
    • TileLink
  • Cores
    • SweRV Cores
  • Tools
    • Verilator
    • FuseSoC
    • Cocotb
    • riscv-dv
  • Chisel 
  • Rocket SoC

GROWING MEMBERSHIP

In March 2019, CHIPS Alliance was formed as a project under the Linux Foundation. The four founding members – Esperanto, Google, SiFive and Western Digital – set the aspirations for the group. CHIPS Alliance can be viewed as an extension of the mission started by organizations such as RISC-V International. RISC-V defines an open instruction set architecture (ISA) specification which paved the way for a plethora of open cores and CPU implementations, but does not instruct how to make the physical hardware and other building blocks needed to create practical open silicon. This is where CHIPS Alliance begins. Using open standards such as RISC-V, CHIPS Alliance is working to collaboratively build robust and industry-proven cores, peripherals and SoCs. 

Early on it became clear that lowering the barriers and cost of development would require collaboration among many parties to develop relevant open source design tools. CHIPS Alliance stepped up to the task. Today the organization focuses on both open source hardware RTL designs and open source software and hardware design tool development. CHIPS Alliance is a barrier free, open organization promoting open silicon.

CHIPS Alliance has grown to nineteen members over the past year. The organization now boasts some of the world’s leading semiconductor manufacturers including Intel, Samsung, Futurewei and Alibaba. Software tools, IP and services companies in the organization include Antmicro, Codasip, Imperas and Qamcom. Several notable universities and open source projects are also part of CHIPS Alliance, including the leading open simulator tool Verilator, UC Berkeley, IIT Madras, Yale University, OpenRoad, Munich University of Applied Sciences and UC San Diego. The complete membership list can be found at https://chipsalliance.org/

HOW DO I GET INVOLVED?

To aid new members and those who are interested in knowing more about CHIPS Alliance, we have created a Getting Started Guide. We encourage everyone to join our main mailing list, follow us on social media channels Twitter and LinkedIn, and engage in our technical community, which is not limited to members. If you see a particular workgroup you want to get involved in, you can join that specific mailing list and attend their meetings.

EVENTS OVER THE PAST YEAR

After the formation of CHIPS Alliance, we began holding events to share what the organization is about and to highlight progress of various work groups. Listed chronologically:

  • It started with our inaugural workshop held in June 2019 at Google’s Sunnyvale campus. The list of speakers included CEOs, CTOs, engineers and other technical presenters. Over 200 attendees joined us for our initial event.
  • In August 2019, CHIPS Alliance held a meetup in the Bay Area highlighting a proposed graphics extension for RISC-V.
  • In November 2019, the Munich University of Applied Sciences held an open source design verification workshop in Munich, Germany.
  • In January 2020, CHIPS Alliance hosted a Chisel Community Conference at Western Digital’s Milpitas office. The two day event featured talks from industry leaders and academia, as well as in-depth training on Chisel, FIRRTL and the associated software ecosystem.
  • In April 2020, CHIPS Alliance held an online meetup on Cache Coherent Memory Fabric with TileLink and OmniXtend. There were over 250 attendees who learned about developments from SiFive, Western Digital and Intel.

TECHNICAL HIGHLIGHTS

  • The CHIPS Alliance announced the enhanced updates of the SweRV Core EH2 and EL2 solutions which were initially developed by Western Digital. The SweRV Core family also includes the EH1. Learn more at GitHub.
  • Antmicro, Google and the CHIPS Alliance have been working together with the lowRISC project to develop Verible support for some SystemVerilog features required for working with practical use cases, such as lowRISC’s ibex. Furthermore, the recent integration of Verible with FuseSoC has made linting and formatting automation even easier.
  • Antmicro and Google developed an open source SystemVerilog test suite. It is available on GitHub. The suite runs a number of open source EDA tools against a series of SystemVerilog compliance tests and presents the results online.
  • The SweRV Support Package (SSP), developed by Codasip in cooperation with Western Digital, provides a comprehensive set of tools and components for designing, implementing, testing and writing software for a SweRV Core-based SoC. The basic version of the SSP is available free of charge at GitHub.
  • The SweRV Instruction Set Simulator (ISS), initially developed by Western Digital, offers full test bench support for the design of SweRV Cores.
  • Antmicro together with Western Digital and FOSSi Foundation developed the initial Verilator open source simulator support in Cocotb – an open source Python coroutine-based co-simulation library.
  • Antmicro has developed an open source test suite for USB IP cores, available on GitHub.
  • The Advanced Interface Bus (AIB) specification and reference implementations from Intel were published on GitHub.
  • Western Digital open sourced the OmniXtend™ cache-coherent protocol to provide an efficient way to attach persistent memory processors. Learn more at GitHub.
  • Google released RISCV-DV – a SystemVerilog/UVM based open-source instruction generator for RISC-V processor verification. The project is available on GitHub.
  • The Cores and Tools workgroups created a portable SoC based on the SweRV CoreTM EH1 using FuseSoC; the SoC includes a debug port and Zephyr support.
  • The Chisel workgroup has also achieved a significant number of technical milestones, as presented on the 2020 Chisel Community Conference

WHY MEMBERS JOIN CHIPS ALLIANCE

The members of CHIPS Alliance join for a variety of reasons. Some organizations join to grow their business. Companies that fall into this group normally offer an open source solution, along with selling support and additional services to interested companies. As an example, Codasip has an open SweRV package that anyone can access, a Pro version with commercial EDA tools, and customization and verification services available upon request.

Many organizations join CHIPS Alliance to accelerate development of a RTL IP/SoC or software tool. For example, Verilator and Chisel are software development tools that have benefited from their organizations joining. See slide 4 of the Verilator, Accelerated presentation to see how CHIPS Alliance has benefited the Verilator ecosystem.

Another reason companies join CHIPS Alliance is to accelerate adoption of IP or software. One such IP is AIB which was brought into CHIPS Alliance by Intel. AIB is a chiplet interconnect and is being adopted by a number of companies. Recently DARPA presented on the benefits of AIB and how chiplets can accelerate SoC development.

A LOOK AHEAD TO 2021

While CHIPS Alliance had a number of in-person events planned for 2020, many of these events have been delayed or postponed due to COVID-19. In the meantime, the CHIPS Alliance will be hosting several online events and meetups. Sign up for our announcements list to be kept up-to-date on our events.

The CHIPS Alliance has seen additional interest from a number of companies, organizations and nonprofits in joining our ecosystem, so we will continue to focus on growing our membership. As development accelerates and more output is generated, we anticipate this will foster even more interest in CHIPS Alliance and its open source solutions.

Lastly, we are actively recruiting a full time executive director and hope to have this individual on board by mid-2020.