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CHIPS SweRV Cores and the Open Tools Ecosystem

By Blog

This post was originally published at Antmicro.

Antmicro’s open source work spans all parts of the computing stack, from software and AI, to PCBs, FPGAs and, most recently, custom silicon. We connect those areas with an overarching vision of open source tooling and methodology, and a software-driven approach that allows us to move fast and build future-centric solutions. Our partners and customers, many of whom work with us also in the context of organizations such as CHIPS Alliance and RISC-V, share our approach to developing open systems. We were recently very happy to be invited to give a talk at the “Production grade, open RISC-V SweRV Core Solutions in CHIPS Alliance” meetup organized by Western Digital where we presented our systems approach on the example of the open source tools ecosystem that targets their SweRV cores and which we are helping to develop.

What is SweRV?

SweRV is a family of production-grade RISC-V implementations originally developed by Western Digital, who have announced they are going to transition 2 billion cores in their products to RISC-V, showing they are fully committed to this open processor architecture. SweRV comes in three variants: the original EH1 and the recently released EH2 and EL2.

EH2 is the world’s first dual-threaded commercial, embedded RISC-V core designed for IoT and AI systems, boasting as much as 6.3 CoreMark/MHz in dual-threaded mode, at 1.2 GHz in 16nm. EL2, on the other hand, is a tiny, low-power but high-performance RISC-V core (with just 0.023 mm2 in 16nm, it runs at up to 600 MHz and 3.6 CoreMark/MHz) targeting applications such as state-machine sequencers and waveform generators. The best thing about them is that anybody can use and extend them for free, with more high performance cores being planned in the future.

But a CPU is as good as the tooling around it and Western Digital knows it. That is why the entire SweRV family was handed over to CHIPS Alliance, which now aims to facilitate using the cores in practical scenarios by maintaining the dynamic ecosystem of relevant tools. Many of the necessary building blocks are already in place, while others are still being developed with active participation of Antmicro, the FOSSi community and others. In this article you will see examples of how you can work with SweRV in simulation, on an FPGA and in an ASIC context.

Getting started

To get started very quickly with no hardware whatsoever, you can simulate any of the SweRV cores in Verilator – one of the most successful and widely used open source projects in the EDA space, which we use extensively. Simply, go to the relevant core’s GitHub space in the CHIPS Alliance organization (e.g. for EH1) and simulate the RTL (which is written in SystemVerilog).

Verilator simulates the RTL with high performance by compiling to an optimized model and running it, outperforming many proprietary alternatives. What is more, it is developing very fast thanks to the work of its maintainer – Wilson Snyder, the FOSSI community and CHIPS Alliance. Antmicro specifically has been working together with Western Digital and Google on adding support for SystemVerilog / Universal Verification Methodology to enable Verilator’s design verification for real-world use cases (see Looking into the future below).

Putting SweRV into an FPGA

If you want to get working on something more tangible, you might want to run SweRV on an FPGA – in a portable, vendor-neutral manner, of course.

To simplify interfacing with various toolchains, simulators and other tools you might need depending on the platform you want to target, you can use Edalize – a Python utility that allows you to seamlessly work with different kinds of EDA tools, both for FPGA and ASIC design. It helps you to maintain consistent workflows and pinpoint whether a specific bug is tool-related or pertains to your code. We’ve been adding quite a lot of new functionalities into Edalize recently, while using it heavily as a default way to interface with various tools out there in our work e.g. sv-tests (again, see Looking into the future for more on that topic).

Edalize will help you use your SweRV-based design on the FPGA/board of your choice without having to care about remembering and maintaining specific configurations and runtime flags.

Another great tool from the same author is FuseSoC, a Python-based package manager and a set of build tools for HDL code. It enables you to reuse your FPGA IP across many designs and, of course, it supports SweRV cores well. Apart from making it simple to reuse existing cores, it allows you to easily create compile-time or run-time configurations, port designs to new targets, set up configurable Continuous Integration as well as let other projects use your code. FuseSoC is also used by the SweRVolf SoC.

Thanks to integrations with other open source tools like Google’s Verible linter/formatter, that we’re also helping to develop, FuseSoC can be used to lint and format System Verilog – we have recently written an article about this.

Incorporating SweRV into an SoC

A core alone, however, is not enough to get any practical work done. If you want to build a System-on-Chip, you should definitely look at LiteX – a SoC generator that allows you to put SweRV in an actual use case. LiteX is an IP library and a SoC builder that is portable between various FPGAs and can turn SweRV into a full blown system. It has a number of IPs and other building blocks such as Ethernet, RAM, UART, SATA, etc. which you can configure to work with different kinds of CPUs. It has initial SweRV support which enables the user to quickly build plug & play SoC systems with SweRV. Antmicro is heavily involved in work to build a robust ecosystem around it. LiteX can run the Zephyr RTOS – which is also supported on SweRV – and, with a suitable CPU, it can run Linux as well. The LiteX SoC ecosystem can also be used together with another tooling project we heavily contribute to, SymbiFlow – the open source FPGA flow.

Simulating, experimenting, testing

If you want to use SweRV to build a full production system and leverage the flexibility to customize that comes with the RISC-V and open tooling, you will most likely need to experiment with the architecture and co-develop hardware and software. This is where Renode can be of immense use thanks to its architectural exploration, simulation, testing and debug capabilities for complex systems: entire SoCs, boards and systems of boards. All you need to do is download Renode and put together a few configuration files – it even comes with many demos and pre-compiled examples for various platforms. Renode provides initial support for SweRV EH1 (with more to come) as well as extensive support of LiteX, which will let you quickly build and simulate entire open source SoCs. On top of that, Renode enables hardware/software co-simulation with Verilator for building your custom IP and testing its HDL as-is, while keeping the rest of the system simulated in Renode to save development time.

Building and verifying a production-grade ASIC

Assuming SweRV fits your use case, you may eventually want to build and verify a production-grade ASIC which includes one of those CPUs. As part of the CHIPS working groups focused on cores and tools, the developers of SweRV in collaboration with Google, Antmicro and others are building an entirely open source design verification ecosystem around the cores family, including projects such as riscv-dv and Whisper ISS. The former is an entire SV/UVM flow based on an instruction generator for RISC-V processor verification, which allows you to perform various tests on SweRV-based designs. It features a number of test suites dedicated to different functionalities. It runs ISS and RTL simulators in tandem and compares the results. Whisper ISS is a tool used for verification of SweRV implementations, which can be run in an interactive mode, allowing the user to single step RISC-V code and inspect/modify the RISC-V registers or system memory, or it can be run in lock-step, e.g. with Verilator.

Looking into the future

There is ongoing work from CHIPS Alliance and the broader open source community to rapidly transform the ASIC-development workflows to fully embrace open source. One such effort is sv-tests, a System Verilog test suite designed to stress-test different kinds of designs in SystemVerilog against various open source tools, showing a results table indicating detailed coverage. SweRV, being written in SystemVerilog, is of course one of the suite’s test targets.

The SV test suite informs some of our ongoing open source work for ASIC tooling, one of the goals of which is to enable open source development and verification of System Verilog designs. An interesting tool to look at in this space is Surelog – a full-blown SystemVerilog parser developed in collaboration between Google and Antmicro oriented at simulation and UVM. We are working to plug it as the System Verilog front-end into various open source tools using a framework called UHDM (Universal Hardware Data Model), which will enable code reuse between various tools with similar needs.

With the recent release of the world’s first open PDK, that we are proud to have been participating in, and the progress being made in the OpenROAD project, which aims at a fully open flow for chip design and other areas, it looks like the future in which a SweRV based SoC can be designed, verified and manufactured using open tools is not that far off.


Apart from being an expanding, production-grade family of cores, SweRV taps into a very good and dynamic ecosystem of tools that we are helping to build. CHIPS Alliance is aiming to revolutionize the way developers work with ASICs and FPGAs by enabling a software-driven approach to silicon, which perfectly aligns with Antmicro’s strategy and long-term objectives. With extensive experience in RISC-V-powered open source work, we offer high-quality services that our customers can use to build on top of SweRV using these new collaborative methodologies and tools. Reach out to Antmicro at to find out how the company can assist you with your next RISC-V-centered project.

Open Source Process Design Kit from Google, SkyWater Technologies and Partners Released

By Blog

This post was originally published at Antmicro.

The ASIC design and manufacturing flow has for a long time been dominated by proprietary tools and processes. The growing complexity of chip-building has been reinforcing the claim that “hardware is too hard to be open source”, as the cost and time needed to build an ASIC have kept small, more agile, software-oriented teams and individuals away from the hardware domain. Thus, ASICs have not been able to benefit from the enthusiasm and collaboration which have been fuelling software development for decades now. Thanks to the continued effort of many entities which Antmicro is very proud to be among, this is now changing quickly.

RISC-V: Openness-driven innovation

The first shift in the walled garden, proprietary chips design landscape came with the creation of the RISC-V Foundation in 2015 centered around the open source RISC-V ISA. Antmicro has been on board as a Platinum Founding Member of the Foundation (now, several hundred members strong, transitioning into a Swiss-based entity called RISC-V International) since the very beginning, as it reflected our belief that an open source approach can – and is bound to, eventually – revolutionize all areas of computing, even the less obvious ones.

RISC-V proved ASIC design can be a collaborative process, with players big and small working together to compliment each other’s strengths not only in developing the ISA but also many of the tools needed to make it practically useful. For example, Microsemi worked with SiFive to provide the SoC complex at the heart of their new and exciting PolarFire FPGA SoC, and then turned to Antmicro to provide a simulation environment – using our open source Renode Framework – to make development possible before the SoC hits the market later this year. The OpenTitan project, driven by key RISC-V adopters Google and Western Digital together with the UK not-for-profit lowRISC, strives to build a more transparent, trustworthy, high-quality reference design and integration guidelines for silicon Root of Trust chips. Such examples abound in the RISC-V world, but the un-core, design tools, verification and other parts of the ecosystem have mostly remained closed.


Established in 2019, CHIPS Alliance takes the open, collaborative aspect of RISC-V even further. CHIPS wants to generate and integrate fully open source, high quality IP and tooling for ASIC design; the organization extends beyond cores and specifications, and acknowledges the importance not only of the result but the process itself; thus, the aim is to make both ASICs and the ASIC design processes open source all the way. Why? Again, a lesson learned from software: if you open up to collaboration, adaptation and change on all levels, the long-term results will be surprisingly good.

CHIPS has been home to such important projects as the Chisel HDL, the Rocket core generator and related tools, the SweRV cores or AIB interconnect. There is work under way to enable fully open source SystemVerilog/UVM support in tools like Verilator and Yosys (with some milestones like fully open source linting, formatting or synthesis of SystemVerilog code already accomplished), opening the door to more open source collaboration around design verification which constitutes the highest cost in modern chip design.

Also in the tools area, the very ambitious OpenROAD project, also a CHIPS member, is a DARPA-backed activity aiming to create a fully open source, quick, automated digital design flow. If you want to see how open source, automated chip design might look like in the future, see OpenROAD’s excellent ChipKit tutorial from ISCA 2020.

Aggregating those activities a vastly different landscape begins to emerge, one where chip design can be innovated upon on various levels, and teams can go back and forth between hardware and software optimizations for new use cases such as machine learning without NDAs and costly licences. But – until now – there was one element notably missing.

First ever open source PDK

We are excited to announce Antmicro’s participation in yet another historic first in the area of semiconductor process technology. In a project led by Google and SkyWater Technology, and in collaboration with partners including Antmicro, Blue Cheetah, efabless and numerous Universities, an open source SkyWater PDK (Process Design Kit) for the 130 nm MOSFET fabrication process, along with related sources, is being made available. This development greatly lowers the cost of entry into chip manufacturing and paves the way for even more exciting collaborations to happen in the open source silicon domain.

For some background, a PDK is a set of data files and tools used to model a specific process in a given foundry used with EDA (Electronic Design Automation) tools in the chip design flow. PDKs traditionally have been closed – to the point where some would say it’s impossible to make them open! This collaboration, where Antmicro worked together with Google and efabless to convert the PDK data for the public release, is an important step towards truly open source chips. The 130nm PDK process is a mature technology that is useful for a range of applications, especially in the area of microcontroller development and research as well as mixed signal embedded designs and other use cases which combine digital and analog circuits. The SKY130 technology stack consists of:

  • 1 level of local interconnect
  • 5 levels of metal
  • Inductor-capable
  • High sheet rho poly resistor
  • Optional MiM capacitors
  • Includes SONOS shrunken cell
  • Supports 10V regulated supply
  • HV extended-drain NMOS and PMOS

SkyWater is an American technology foundry accredited by the US Department of Defense, which offers custom integrated circuit design and manufacturing services. It is predicted that the launch of the open source SKY130 process node will be followed by other, more advanced nodes, ultimately enabling more advanced processor applications, including ones that are Linux-capable.

The inaugural talk by Tim Ansell

On Tuesday, June 30 at 16:00 GMT, Google’s Tim Ansell will give a talk at the FOSSi Dial-up meeting, presenting a thorough overview of the technical details of the PDK, as well as outlining the project’s goals and its roadmap. The event will be livestreamed on YouTube and will be followed by a Q&A session, so tune in to find out more about this historic step towards an open, accessible and collaborative chip-making process.

Semiconductor Engineering: About The SweRV Core EH2

By Blog

In mid-May, CHIPS Alliance announced the open sourcing of the SweRV Core EH2 and SweRV Core EL2 designed by Western Digital. These cores, as well as the earlier EH1, are now supported by Codasip’s SweRV Core Support Package which provides all of the components necessary to design, implement, test, and write software for a SweRV Core-based system-on-chip. But what is SweRV Core EH2?

The SweRV Core EH1 was the first to be released through CHIPS Alliance and was a core aimed at high-end embedded applications including Western Digital’s flash controllers and SSDs. The core is a dual issue, superscalar, high-performance core with 9 pipeline stages. The EH2 is an exciting further development aimed at delivering even more performance for IoT, artificial intelligence and data-intensive embedded applications.

To read more, please check out the article at Semiconductor Engineering written by Roddy Urquhart at Codasip:

QuickLogic Announces Open Reconfigurable Computing Initiative

By Blog

Originally issued by QuickLogic, the following press release announces the QORC initiative including the world’s first vendor-supported open FPGA toolchain using SymbiFlow, and describes the contribution of CHIPS Alliance members Antmicro and Google.

  • QuickLogic Open Reconfigurable Computing (QORC) initiative, developed by Antmicro in collaboration with QuickLogic and Google, broadens access to company’s FPGA technology and eFPGA IP for all embedded systems developers
  • First Programmable Logic Company to Embrace Open Source FPGA Development Tools

San Jose, CA – June 16, 2020 – QuickLogic Corporation (NASDAQ: QUIK), a developer of ultra-low power multi-core voice-enabled SoCs, embedded FPGA IP, and Endpoint AI solutions, today announced its ground breaking QORC (QuickLogic Open Reconfigurable Computing) initiative, making it the first programmable logic vendor to actively embrace a fully open source suite of development tools for its FPGA devices and eFPGA technology. This initiative engenders the emerging trend toward open source tooling, significantly broadens access to the company’s products, and enables both hardware and software developers with tools supported by both the user community and QuickLogic.The company’s initial open source development tools, developed by Antmicro in collaboration with QuickLogic and Google, include complete support for its EOS S3 low power voice and sensor processing MCU with embedded FPGA, and its PolarPro 3E discrete FPGA family. Support for additional QuickLogic products, including QuickAI and support for its eFPGA IP offering will be added over the next few months.

EOS S3 Open Source Development Tools:

  • FPGA Development Flow: SymbiFlow – Open source tools for the optimization and automation of the FPGA design flow, from Verilog to bitstream generation. These tools enable innovation by making FPGAs more accessible to a broader community.
  • SoC Emulation: Renode – Antmicro’s Renode is an open source simulation framework for rapid prototyping, development and testing of multi-node systems. Utilizing Renode gives developers the flexibility to fully evaluate multiple development board applications.
  • Zephyr Real Time Operating System (RTOS) – The Zephyr RTOS is an open source, vendor-neutral, compact, real-time operating system running on the Arm Cortex® M4F for connected, resource-constrained and embedded devices in applications that require security and safety.
  • QuickFeather Development Kit – A small form factor, 100% open source hardware development kit ideal for the next generation of low-power Machine Learning (ML) capable IoT devices.

Traditionally, programmable logic vendors offered and supported only proprietary synthesis, place and route tools. Open source tools were relegated to hobbyists, academics, and independent consultants. However, the electronics industry is starting to see a shift toward open sourced hardware and software as it provides flexibility, vendor and community support, longevity, and adaptability to each engineer’s design flow. Google and Antmicro have been noteworthy influencers in this market, increasing the breadth of supported architectures and quality of results for the open source tools. They are now not only viable but desirable for the majority of the development community, including design teams at many of the industry’s largest companies.

“QORC is QuickLogic’s initiative to embrace the rapidly growing open source FPGA tooling ecosystem, inspiring engineers to collaborate on the creation of exciting and innovative products,” said Brian Faith, QuickLogic’s president and CEO. “We believe that the wide adoption of open source tools represents a paradigm shift for the industry, and we’re proud to be at the leading edge.”

“With its open source-centered approach, Antmicro has been moving the technological frontier, building whole ecosystems of non-proprietary solutions and overcoming the limitations inherent in closed technologies,” said Michael Gielda, Antmicro’s VP of Business Development. “We’ve been excited to participate in this historical first from QuickLogic, by contributing our expertise in software, hardware and tools to implement the necessary SymbiFlow, Renode and Zephyr support for their hardware platform – broadening their reach within the developer community.”


SymbiFlow FPGA, Renode SoC Emulation, and Zephyr RTOS support are available now for QuickLogic’s EOS S3 voice and sensor processing platform and PolarPro 3E FPGA products, as well as the new QuickFeather Development Kit. Support for QuickLogic’s embedded FPGA technology will be added later this year. To learn more, please visit

About QuickLogic

QuickLogic Corporation (NASDAQ: QUIK) is a fabless semiconductor company that develops low power, multi-core semiconductor platforms and Intellectual Property (IP) for Artificial Intelligence (AI), voice and sensor processing. The solutions include embedded FPGA IP (eFPGA) for hardware acceleration and pre-processing, and heterogeneous multi-core SoCs that integrate eFPGA with other processors and peripherals. The Analytics Toolkit from our recently acquired wholly-owned subsidiary, SensiML Corporation, completes the end-to-end solution with accurate sensor algorithms using AI technology. The full range of platforms, software tools and eFPGA IP enables the practical and efficient adoption of AI, voice, and sensor processing across mobile, wearable, hearable, consumer, industrial, edge and endpoint IoT. For more information, visit and

QuickLogic and logo are registered trademarks and EOS and SensiML are trademarks of QuickLogic. All other trademarks are the property of their respective holders and should be treated as such.

Press Contact:

Andrea Vedanayagam
Veda Communications

A Look Back at the CHIPS Alliance’s Incredible Growth

By Blog

It’s been just over a year since the CHIPS Alliance was founded with the mission of making open source hardware development more accessible to companies, universities and individuals. We’re working to bring the dynamics of the hugely successful open source software development model into ASIC design, building on the groundwork set by the RISC-V community. Progress over the past year is detailed in our Annual Report

 CHIPS Alliance is focused on expanding on this open hardware vision by:

  • Targeting other parts of ASICs beyond the CPU core, gradually open sourcing all IPs that go into a SoC, both analog and digital.
  • Open sourcing the tools needed to work with ASICs, making it possible to design innovative solutions without a massive upfront investment.
  • Providing real, battle-proven reference implementations and project infrastructure to ensure the continued success of the projects we govern and support.

 With these three pillars guiding our efforts, we believe that the CHIPS Alliance will enable truly open hardware to flourish for the first time. The CHIPS Alliance has already made incredible progress so far. We have achieved a number of important technical milestones, including announcing newly enhanced SweRV Cores – EH2 and EL2 – and releasing the Advanced Interface Bus (AIB) specification and reference implementations by one of the CHIPS Alliance’s newest members, Intel. These technical accomplishments are making it easier for engineers to design innovative embedded applications for the latest computing requirements.

We’re also excited by the significant community interest in the work we’re doing. Hundreds of people from around the world have attended CHIPS Alliance events over the past year, both in-person and online, and our working groups are running full steam ahead. Check out our Annual Report to learn more about the CHIPS Alliance’s news and activities, and stay up to date by following us on Twitter and LinkedIn.

SystemVerilog Linting and Formatting with FuseSoC – Verible Integration

By Blog

This post was originally published at Antmicro.

Although new ASIC design methodologies and tools such as Chisel are on the rise, most ASIC projects still use SystemVerilog, the support of which in open source tools has traditionally lagged behind. This is unfortunate, as using proprietary alternatives with the CI systems of open source projects is neither scalable due to licensing costs and restrictions nor simple due to the need for license management and obfuscation.

Antmicro, Google and the CHIPS Alliance, which we are members of, have been working together with the lowRISC project to address this issue by implementing relevant tools and useful integrations in the open source domain. One large milestone on this route is Verible, an open source Flex/YACC SystemVerilog parser, linter and formatter recently open sourced by our partner and customer, Google.

Among other developments in that space, Antmicro has been helping to make Verible support some SystemVerilog features required for working with practical use cases, such as lowRISC’s ibex, a 32-bit RISC-V core used in the open source security project, OpenTitan. But to generate adoption, ease of use is just as important as features, which is why Verible was recently exposed to a wider audience by integrating it with FuseSoC.

One of the main advantages of an open source linter/formatter is how easy it is to integrate it with existing workflows of open source projects. As it happens, many open source FPGA/ASIC projects, including OpenTitan, are managed with FuseSoC, an open source tooling and IP package manager (from our fellow FOSSi veteran Olof Kindgren) which we also use and support. Thanks to the integration of Verible with FuseSoC, linting and formatting automation becomes much easier.

Below you will find a simple example and explanation of how to use the integration The example contains an accompanying CI setup which you can mimic in your own project.


We will use the following example repository to explain the usage of Verible with FuseSoC.
We will show how to build Verible binaries, download ibex – a small 32 bit RISC-V CPU core – and run FuseSoC to perform linting/formatting using Verible.


Install the prerequisites (tested on Ubuntu 18.04):

sudo apt update
sudo apt install cmake ninja-build wget python3 python3-pip python3-setuptools make tar git
sudo pip3 install fusesoc

Building Verible

Verible can be built using the Bazel build system.
Bazel is not available in the debian/ubuntu apt repositories. To install Bazel you should add Bazel’s apt repository:

curl | sudo apt-key add -
echo "deb [arch=amd64] stable jdk1.8" | sudo tee /etc/apt/sources.list.d/bazel.list
sudo apt update && sudo apt install bazel

To build Verible, a C++11 compatible compiler is required. After the installation of bazel, Verible can be built and installed:

git clone
cd Verible
bazel build -c opt //...
bazel run :install -c opt -- `pwd`/../Verible_bin
export PATH=`pwd`/../Verible_bin/:$PATH

Alternatively, you can download pre-built Verible binaries from the Verible release page. Refer to the Verible documentation and Bazel installation instructions for more details.

Running Verible tools with FuseSoC

FuseSoC uses tool backends available in edalize, which is another workflow automation project from the same author that we contribute to regularly. In order to use the Verible tools with FuseSoC you need to define a tool section in the FuseSoC core target file. Ibex already includes the integration, so you can use its ibex_core.core file as an example.

Verible linter with FuseSoC on ibex

To perform linting in ibex_core, use:

git clone
cd ibex
#add Verible lint rules
sed -i '132i\          - "-generate-label"\n          - "-unpacked-dimensions-range-ordering"\n          - "-explicit-parameter-storage-type"\n          - "-line-length"\n          - "-module-filename"\n          - "-no-trailing-spaces"\n          - "-undersized-binary-literal"\n          - "-struct-union-name-style"\n          - "-case-missing-default"\n          - "-explicit-task-lifetime"\n          - "-explicit-function-lifetime"' ibex_core.core

fusesoc --cores-root. run --target=lint --tool=veriblelint lowrisc:ibex:ibex_core:0.1

Verible formatter with FuseSoC on ibex

To format the ibex_core with Verible:

#add Veribleformat rules
sed -i '154i\          - "--max_search_states"\n          - "10000000"' ibex_core.core
fusesoc --cores-root . run --target=format --no-export lowrisc:ibex:ibex_core:0.1

The demo also shows how the Verible linter can be incorporated into CI pipelines for automatic detection of lint errors. To demonstrate that, a Pull Request containing an intentional lint error has been opened. An automatically executed CI pipeline was able to detect the issues with the code and inform the developers about the failed build status. The output of the lint command can provide useful information about a possible cause of the error. Early detection of lint errors can reduce the number of bugs and improve the overall code quality. Using a linter can accelerate development and reduce costs by finding errors at an early stage of the process. Moreover, incorporating the Verible formatter in CI can also ensure that incoming contributions automatically employ the project’s coding style.

More detailed instructions regarding building and using Verible with FuseSoC can be found in the README file located in the demo repository.

If you are involved in FPGA and ASIC development and want your project to be portable, modular and harness other benefits of a software-driven, open-source-based approach, Antmicro is there to help. As a key service provider in both RISC-V Foundation and CHIPS Alliance, we have lots of readily available SoC building blocks, tools and capabilities to assist you in developing your next product or platform.

Open Source USB test suite

By Blog

Note: the open source test suite will be demonstrated at the CHIPS Alliance booth at the RISC-V Summit 2019 – join us Dec 10-12 in the San Jose Convention Center!

USB is often a daunting topic for developers, and implementing support for it from scratch is a time consuming task. When the expected result is more complicated than a USB-to-serial bridge, the solution would be to either use a hardware transceiver or, especially for older USB standards, use an open source core to implement one directly in the FPGA fabric. But which core to use?

There are many different USB IP cores available, implemented in languages ranging from traditional HDLs like Verilog to modern alternatives like migen (or its new variant, nmigen). Most of them come with their own set of test cases, often checking their internal mechanisms and not corresponding directly to those in other projects. What was lacking is a unified test suite that would run each core through the same set of scenarios, providing a direct, apples-to-apples comparison of their behavior.

A solution from Antmicro, a CHIPS Alliance Gold member, is an open source test suite for USB IP cores, available on their Github. It currently supports USB1.1 and will be extended for higher revisions in the future.

In the test suite, Antmicro is making use of several open source technologies that they have come to appreciate through other projects. The tests are implemented using Cocotb and the low-level details are handled by the newly created cocotb_usb package. This means that even complicated tests, like those that verify the enumeration procedure under different OSes can be written with easy to understand, Python syntax.

from cocotb_usb.harness import get_harness
from cocotb_usb.device import UsbDevice
from cocotb_usb.descriptors import Descriptor

def test_enumeration(dut):
    harness = get_harness(dut)
    yield harness.reset()
    yield harness.connect()

    yield Timer(1e3, units="us")

    yield harness.port_reset(1e3)
    yield harness

    yield harness.set_device_address(DEVICE_ADDRESS)

Test suite architecture

As the various IP cores often provide different interfaces towards the user, from different kinds of FIFOs to expected signals to drive the bidirectional USB pins, they are wrapped in a unified layer to create a simple SoC, also written in Python using LiteX. It provides various helper blocks and takes care of the bus infrastructure, clocking and reset logic, generating Verilog output for the whole system ready to be tested under any number of open source simulators. A minimalistic testbench file provides a unified interface as the top object for the simulation.

USB testing diagram

Python package

At the heart of the test suite is cocotb_usb, a Python package providing API for sending and receiving various USB packets, handling low-level bus states, verifying descriptor contents and checking timings. This is done by providing a UsbTest object that acts as a host and interacts with the device under test. Depending on your needs, you can output single packets, use whole transactions with e.g. automated retries upon receiving “not acknowledged” tokens, or just use high-level functions like get_config_descriptor() and let the library handle all the details. Meanwhile, the UsbDevice class provides means to store all of the descriptors that the core can report in an organized way.

The test results can be viewed in a standard Cocotb XML results file, the behavior of all signals in the system at all points can be checked in a VCD signal dump (to be viewed e.g. in GTKWave) and we use open source sigrok decoders to obtain packets and transactions, to be exported for viewing in Wireshark.

Test results in GTKWave

Current checks

Currently tested cores are:

  • ValentyUSB – CPU-less IP core written in LiteX, using the eptri interface
  • Foboot – target with VexRiscv CPU running bare-metal Foboot firmware (it utilizes the epfifo interface of the ValentyUSB core)
  • usb1_device – a USB1.1 IP core developed by in Verilog
  • TinyFPGA USB bootloader – IP core written in Verilog with interesting features, like providing an interface to program SPI flash memory over USB
  • tnt`s USB IP core – target with a PicoRV32 CPU, running bare-metal firmware interfacing with the Verilog IP core

So, what tests are supported? They range from a simple control packet handling with both single and multiple transfers, through handling SOF packets, validating clock recovery in the presence of an imperfect clock signal, to complex enumeration scenarios under Linux, Windows 10 and macOS. There are also some special cases, like testing the ValentyUSB core without a CPU by configuring it through a Wishbone bus, or verifying behavior of the TinyFPGA-Bootloader by using CDC transfers to send a boot command to the core.


While full blown documentation is coming soon, there are ways to get involved right now:

  • First, to run the test suite, go to the repository and follow the steps in the README,
  • To write your own test, take a look at our tests folder and the functions provided by the UsbTest class,
  • To run the tests on another IP core, you will need to prepare a simple LiteX wrapper, a config file with expected descriptor values that the core will return and a Makefile that will point to the needed files and provide the needed steps,
  • If you would like to test a different USB class that your target supports, head to the cocotb_usb repository and feel free to extend it with that class’ descriptors and requests.

Podcast – Embedded Computing Design – Five Minutes With… Zvonimir Bandic, Chairman, Chips Alliance

By Blog

Zvonimir Bandic wears lots of hats. He is the Senior Director of Hardware Platforms for Western Digital; he’s a Member of the Board of Directors for the RISC-V Foundation, and he’s the Chairman of the Chips Alliance. It’s that latter capacity that we discussed in this week’s Five Minutes With…discussion. The organization focuses on things like open source hardware, software tools, RTL development, and related topics. They will be holding their inaugural workshop in just a few weeks, so it was timely to understand the purpose of the Alliance. And now I do, as will you.

Listen to the Podcast »