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Announcement

Efabless Joins CHIPS Alliance to Accelerate the Growth of the Open Source Chip Ecosystem

By Announcement

Efabless to give a talk on the OpenROAD project at the CHIPS Alliance Workshop on Sept. 17

SAN FRANCISCO, Sept. 15, 2020 – CHIPS Alliance, the leading consortium advancing common and open hardware for interfaces, processors and systems, today welcomed Efabless, a crowdsourcing design platform for custom silicon, as its latest member. Efabless is already an active participant in several open source initiatives that the CHIPS Alliance is involved in, including the OpenROAD project and the Open Source Shuttle Program.

“The mission of the CHIPS Alliance to democratize silicon design nicely aligns with our focus on changing how chip design is done forever. Our platform is essentially an ecosystem-in-a-box that’s instantly accessible to designers anywhere to create and deliver new chip solutions faster than traditional approaches,” said Mohamed Kassem, co-founder and CTO at Efabless. “Through the CHIPS Alliance and other open source initiatives, we’re working to make it easier for design teams of all sizes to define, develop, collaborate and monetize their work.” 

At the CHIPS Alliance Workshop on Thursday, Sept. 17, Kassem and Andrew Kahng of OpenROAD and UCSD will be presenting the session “OpenROAD open RTL-to-GDS update.” The talk will discuss the OpenROAD autonomous and fully open flow for chip design.

“We’ve been impressed with Efabless’ strong commitment to accelerating open source chip innovation,” said Dr. Zvonimir Bandić, Chairman, CHIPS Alliance. “We look forward to working closely with Efabless and our other members to continue to lower the cost of developing IP and tools for hardware development.”

Efabless is collaborating with SkyWater Technology Foundry  and CHIPS Alliance members Google and Antmicro on an open source SkyWater PDK (Process Design Kit) for the 130 nm CMOS process technology. Efabless will make the design for this PDK simple and affordable by integrating resources on its cloud-based design platform including: an open source based end-to-end ASIC design flow – openLANE based on OpenROAD, Yosys and Magic; the open source striVe family of full ASIC reference designs; and a marketplace for monetizing chip and IP designs. This project will help lower the cost of entry for chip manufacturing, making chip design more accessible for everyone. 

Additionally, Efabless is managing the Open Source Shuttle Program sponsored by Google. This program will provide free of cost chip manufacturing runs for open source designs. The first run is scheduled for November 2020, and another will take place in early 2021.

To check out the schedule for the CHIPS Alliance Workshop and register for this free event, please visit: https://events.linuxfoundation.org/chips-alliance-workshop/program/schedule/.  

About the CHIPS Alliance

The CHIPS Alliance is an organization which develops and hosts high-quality, open source hardware code (IP cores), interconnect IP (physical and logical protocols), and open source software development tools for design, verification, and more. The main aim is to provide a barrier-free collaborative environment, to lower the cost of developing IP and tools for hardware development. The CHIPS Alliance is hosted by the Linux Foundation. For more information, visit chipsalliance.org.

About the Linux Foundation

The Linux Foundation was founded in 2000 and has since become the world’s leading home for collaboration on open source software, open standards, open data, and open hardware. Today, the Foundation is supported by more than 1,000 members and its projects are critical to the world’s infrastructure, including Linux, Kubernetes, Node.js and more. The Linux Foundation focuses on employing best practices and addressing the needs of contributors, users, and solution providers to create sustainable models for open collaboration. For more information, visit linuxfoundation.org.

 

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CHIPS Alliance Welcomes Mentor as its Newest Member

By Announcement

Mentor to present at the virtual CHIPS Alliance Workshop on Sept. 17 

SAN FRANCISCO, Aug. 18, 2020 – CHIPS Alliance, the leading consortium advancing common and open hardware for interfaces, processors and systems, today announced that Mentor, a Siemens business, has joined as its newest member. The CHIPS Alliance has a roster of more than 20 members collaborating to accelerate the creation and deployment of open system-on-chips (SoCs), peripherals and software tools for a wide range of applications.

“Mentor has a long history of supporting open standards to enable companies to design and verify their solutions,” said Badru Agarwala, general manager of Digital Design and Implementation Solutions at Mentor. “High level synthesis plays an important role in the design of accelerators, and in fostering an open and collaborative hardware development ecosystem. We look forward to contributing to the CHIPS Alliance’s efforts to reduce design barriers for the benefit of the entire silicon ecosystem.”

Mentor is a world leader in electronic hardware and software design solutions, providing products, consulting services and award-winning support for the world’s most successful electronic, semiconductor and systems companies. The company recently collaborated with another CHIPS Alliance member, Imperas Software, to extend the hardware design verification of RISC-V cores with industrial quality coverage methodologies. Mentor’s high level synthesis (HLS) tool, Catapult, enables hardware designers to use C++ or SystemC to describe functional intent and move up to a more productive abstraction level.

 “Over the past year we’ve focused on expanding our membership base and achieving new technical milestones as we work to make open source silicon a reality for mobile, computing, consumer electronics and Internet of Things applications,” said Dr. Zvonimir Bandić, Chairman, CHIPS Alliance. “We’re pleased to welcome Mentor to this dynamic, collaborative community driving the new era of hardware innovation.” 

Mentor will be presenting at the CHIPS Alliance Workshop, being held virtually on Thursday, Sept. 17. Mentor’s Anoop Saha will be presenting the session “Open ML Accelerator.” 

To see the full CHIPS Alliance Workshop schedule and register for the event, please visit: https://events.linuxfoundation.org/chips-alliance-workshop/program/schedule/.

To learn more about CHIPS Alliance’s work, please check out the 2020 Annual Report: https://chipsalliance.org/chips-alliance-2020-annual-report/

About the CHIPS Alliance

The CHIPS Alliance is an organization which develops and hosts high-quality, open source hardware code (IP cores), interconnect IP (physical and logical protocols), and open source software development tools for design, verification, and more. The main aim is to provide a barrier-free collaborative environment, to lower the cost of developing IP and tools for hardware development. The CHIPS Alliance is hosted by the Linux Foundation. For more information, visit chipsalliance.org.

About the Linux Foundation

The Linux Foundation was founded in 2000 and has since become the world’s leading home for collaboration on open source software, open standards, open data, and open hardware. Today, the Foundation is supported by more than 1,000 members and its projects are critical to the world’s infrastructure, including Linux, Kubernetes, Node.js and more. The Linux Foundation focuses on employing best practices and addressing the needs of contributors, users, and solution providers to create sustainable models for open collaboration. For more information, visit linuxfoundation.org.

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Note: A list of relevant Siemens trademarks can be found here.

 

QuickLogic Joins CHIPS Alliance to Expand Open Source FPGA Efforts

By Announcement

QuickLogic to present at the virtual CHIPS Alliance Workshop on Sept. 17 

SAN FRANCISCO, Aug. 11, 2020 – CHIPS Alliance, the leading consortium advancing common and open hardware for interfaces, processors and systems, today announced that QuickLogic Corporation (NASDAQ: QUIK), a developer of ultra-low power multi-core voice-enabled SoCs, embedded FPGA IP, and Endpoint AI solutions, has joined as its newest member.

“Over the past few years the electronics industry has seen a big shift towards open source hardware and software, and we’re proud to be one of the companies at the forefront of that movement,” said Brian Faith, president and CEO at QuickLogic. “We have already been working closely with several CHIPS Alliance members to make FPGA tools and devices more accessible, and we look forward to continuing these efforts as an official member of the organization.”

QuickLogic recently announced the QuickLogic Open Reconfigurable Computing (QORC) initiative to broaden access to open FPGA technology for embedded systems developers. QuickLogic’s initial open source development tools, developed in collaboration with CHIPS Alliance members Antmicro and Google, include complete support for QuickLogic’s EOS S3 low power voice and sensor processing MCU with an integrated embedded FPGA (eFPGA), and its PolarPro 3E discrete FPGA family. 

Additionally, QuickLogic and Antmicro launched the first fully open source Arm Cortex M4 MCU + eFPGA SoC dev kit, QuickFeather™. Antmicro added support for the QuickFeather dev kit into the Zephyr Real Time Operating System (RTOS), as well as in its open source Renode simulation framework. This small form factor development board is ideal for low-power machine learning (ML) capable IoT devices.

Said Dr. Zvonimir Bandić, Chairman, CHIPS Alliance: “The CHIPS Alliance is continuing to focus on expanding its member base with organizations from a diverse set of industries. QuickLogic, a leader in open source eFPGA IP and FPGA tooling, will help us drive innovation in the FPGA sector and further our mission to remove barriers for open hardware design.”

QuickLogic’s Brian Faith will present “Open Source FPGA Tooling, Our Journey from Resistance to Adoption” at the CHIPS Alliance Workshop, being held virtually on Thursday, September 17.

To see the full CHIPS Alliance Workshop schedule and register for the event, please visit: https://events.linuxfoundation.org/chips-alliance-workshop/program/schedule/.

About the CHIPS Alliance

The CHIPS Alliance is an organization which develops and hosts high-quality, open source hardware code (IP cores), interconnect IP (physical and logical protocols), and open source software development tools for design, verification, and more. The main aim is to provide a barrier-free collaborative environment, to lower the cost of developing IP and tools for hardware development. The CHIPS Alliance is hosted by the Linux Foundation. For more information, visit chipsalliance.org.

About the Linux Foundation

The Linux Foundation was founded in 2000 and has since become the world’s leading home for collaboration on open source software, open standards, open data, and open hardware. Today, the Foundation is supported by more than 1,000 members and its projects are critical to the world’s infrastructure, including Linux, Kubernetes, Node.js and more. The Linux Foundation focuses on employing best practices and addressing the needs of contributors, users, and solution providers to create sustainable models for open collaboration. For more information, visit linuxfoundation.org.

 

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CHIPS Alliance Announces AIB 2.0 Draft Specification to Accelerate Design of Open Source Chiplets

By Announcement

AIB reduces design barriers, costs, and leverages generators to ease development of  chiplet-based designs

SAN FRANCISCO, July 16, 2020 – CHIPS Alliance, the leading consortium advancing common and open hardware for interfaces, processors and systems, today announced that it has released the Advanced Interface Bus (AIB) version 2.0 draft specification on GitHub. The AIB standard is an open-source, royalty-free PHY-level standard for connecting multiple semiconductor die within the same package. AIB is ideal for designing SoCs, FPGAs, SerDes chiplets, high-performance ADC/DAC chiplets, optical networking chiplets and more. 

AIB 2.0 has more than six times the edge bandwidth density of AIB 1.0 through increases in the per-wire line rate and the number of IOs per channel. Additionally, with smaller microbumps AIB 2.0 can use as little as half of the current microbump array area. AIB makes it easier for designers to connect chiplets so companies can mix foundries, process nodes, IP sources, etc. for more flexibility in designing highly-integrated semiconductor devices. 

“The AIB 2.0 draft standard continues the CHIPS Alliance’s efforts to provide comprehensive design resources to simplify hardware design and reduce development costs,” said Dr. Zvonimir Bandić, Chairman, CHIPS Alliance. “As companies increasingly rely on chiplets to keep up with the latest computing requirements and workloads for different applications, AIB will make it easier to integrate silicon IP with other chiplets into a single device to deliver new levels of functionality and optimization.”

The CHIPS Alliance and its members are working together to help foster the growth of an industry ecosystem which engenders more device innovation via heterogeneous integration. With broader adoption and support for AIB-enabled chiplets, developers can go beyond the limits of traditional monolithic semiconductor manufacturing to leverage the ideal process node for each function in their design while lowering development costs. The AIB specification is already in use by leading semiconductor companies, and has also been adopted by DARPA’s Common Heterogeneous Integration and IP Reuse Strategies (CHIPS) program.

To further reduce the design effort of producing block variants and porting custom blocks to a new process, Blue Cheetah Analog Design, Inc. has developed agile, process portable, and parameterizable generators for the AIB die-to-die interface. Blue Cheetah’s AIB PHY Generator enables the rapid generation of sign-off ready AIB custom blocks (i.e. netlist, GDS, LEF, LIB, and behavioral models) across a multitude of process design kits (PDKs).

“Reducing barriers to entry in developing custom silicon will be critical for the growth, adoption, and success of the chiplet movement,” said Dr. Krishna Settaluri, CEO, Blue Cheetah Analog Design. “By producing custom blocks at push-button speed, Blue Cheetah’s generators drastically reduce time-to-market and engineering effort required to produce tape-out ready IP. We are excited to offer this capability and look forward to enabling companies to thrive in the chiplet ecosystem.”

Dr. Settaluri of Blue Cheetah and David Kehlet of Intel® Corporation will be discussing the AIB PHY generator and AIB 2.0 draft specification at DAC 2020, which is being held virtually this year. The session, called “Tutorial 10 Part 1: Chiplet Integration: Tools, Methodology, Requirement, Infrastructure,” will take place on Monday, July 20 at 1:30 p.m. PT. To learn more about the talk, please visit here

To read the AIB specification, please visit: https://github.com/chipsalliance/AIB-specification.

To check out the AIB PHY Generator, please visit: https://github.com/chipsalliance/aib-phy-generator

About the CHIPS Alliance

The CHIPS Alliance is an organization which develops and hosts high-quality, open source hardware code (IP cores), interconnect IP (physical and logical protocols), and open source software development tools for design, verification, and more. The main aim is to provide a barrier-free collaborative environment, to lower the cost of developing IP and tools for hardware development. The CHIPS Alliance is hosted by the Linux Foundation. For more information, visit chipsalliance.org.

About the Linux Foundation

The Linux Foundation was founded in 2000 and has since become the world’s leading home for collaboration on open source software, open standards, open data, and open hardware. Today, the Foundation is supported by more than 1,000 members and its projects are critical to the world’s infrastructure, including Linux, Kubernetes, Node.js and more. The Linux Foundation focuses on employing best practices and addressing the needs of contributors, users, and solution providers to create sustainable models for open collaboration. For more information, visit linuxfoundation.org.

 

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CHIPS Alliance’s Newly Enhanced SweRV Cores Available to All for Free

By Announcement

CHIPS Alliance to host online event to help community innovating with SweRV Core EH2 and EL2 Solutions

SAN FRANCISCO, May 14, 2020 – CHIPS Alliance, the leading consortium advancing common and open hardware for interfaces, processors and systems, today announced new enhancements to the SweRV Core™ EH2 and SweRV Core EL2, developed for the open-source community by Western Digital. Since the introduction of the cores earlier this year, the CHIPS Alliance has worked with its community to exhaustedly validate the cores through a transparent and rigorous process, as well as incorporate a variety of new updates.

The SweRV Core EH2, the world’s first dual-threaded, commercial, embedded RISC-V core, is designed for embedded devices supporting data-intensive edge, artificial intelligence (AI) and Internet of Things (IoT) applications. SweRV Core EL2 is an ultra-small, ultra-low-power RISC-V core optimized for applications such as state-machine sequencers and waveform generators. The newly updated cores are now available to everyone for free.

CHIPS Alliance will host an online event to discuss the SweRV Core EH2 and EL2, along with the available software support and solutions for programmers on May 20, 2020 at 5:30 p.m. PT. The event will feature talks from representatives of Antmicro, CHIPS Alliance, Codasip, Metrics and Western Digital.

“Our work to help bring the newly enhanced SweRV Core EL2 and EH2 to the open hardware community demonstrates key progress towards our goal of accelerating RISC-V innovation. We’ve already seen significant industry interest in the SweRV Core EH1 and are pleased to offer two compelling additional options to engineers designing IoT, consumer, mobile and other embedded applications,” said Dr. Zvonimir Bandić, Chairman, CHIPS Alliance.

To register for the CHIPS Alliance virtual event on May 20, please visit: https://zoom.us/webinar/register/WN_fbjiN5uvSuGbGdWUGlI65g.

To learn more about the SweRV Cores, please visit: https://github.com/chipsalliance/Cores-SweRV.

About the CHIPS Alliance

The CHIPS Alliance is an organization which develops and hosts high-quality, open source hardware code (IP cores), interconnect IP (physical and logical protocols), and open source software development tools for design, verification, and more. The main aim is to provide a barrier-free collaborative environment, to lower the cost of developing IP and tools for hardware development. The CHIPS Alliance is hosted by the Linux Foundation. For more information, visit chipsalliance.org.

About the Linux Foundation

The Linux Foundation was founded in 2000 and has since become the world’s leading home for collaboration on open source software, open standards, open data, and open hardware. Today, the Foundation is supported by more than 1,000 members and its projects are critical to the world’s infrastructure, including Linux, Kubernetes, Node.js and more. The Linux Foundation focuses on employing best practices and addressing the needs of contributors, users, and solution providers to create sustainable models for open collaboration. For more information, visit linuxfoundation.org.

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Intel joins CHIPS Alliance to promote Advanced Interface Bus (AIB) as an open standard

By Announcement

Open development for SOCs gets major boost with new collaboration

SAN FRANCISCO, Jan. 22, 2020 /PRNewswire/ — CHIPS Alliance, the leading consortium advancing common and open hardware for interfaces, processors and systems, today announced industry leading chipmaker Intel as it’s newest member. Intel is contributing the Advanced Interface Bus (AIB) to CHIPS Alliance to foster broad adoption. 

CHIPS Alliance is hosted by the Linux Foundation to foster a collaborative environment to accelerate the creation and deployment of open SoCs, peripherals and software tools for use in mobile, computing, consumer electronics and Internet of Things (IoT) applications. The CHIPS Alliance project develops high-quality open source Register Transfer Level (RTL) code and software development tools relevant to the design of open source CPUs, SoCs, and complex peripherals for Field Programmable Gate Arrays (FPGAs) and custom silicon. 

Intel is joining CHIPS Alliance to share the  Advanced Interface Bus (AIB) as an open-source, royalty-free PHY-level standard for connecting multiple semiconductor die within the same package. This effort is intended to encourage an industry environment in which silicon IP can be developed using any semiconductor process as a “chiplet,” and easily integrated with other chiplets into a single device to deliver new levels of functionality and optimization. Broader adoption and support for AIB-enabled chiplets will help device developers grow beyond the limits of traditional monolithic semiconductor manufacturing and reduce the cost of development. Working together, Intel and CHIPS Alliance will encourage the growth of an industry ecosystem which engenders more device innovation via heterogeneous integration.

The AIB specifications and collateral will be further developed in the Interconnects workgroup.  The group will begin work imminently to make new contributions to foster increased innovation and adoption.  All AIB technical details will be placed in the CHIPS Alliance github. In addition, Intel will have a seat on the governing board of CHIPS Alliance. Go to www.chipsalliance.org to learn more about the organization or to join the workgroup mailing list.  

“We couldn’t be more happy to welcome Intel to CHIPS Alliance.” said Dr. Zvonimir Bandić, Chairman, CHIPS Alliance, and senior director of next-generation platforms architecture at Western Digital.   “Intel’s selection of CHIPS Alliance for the AIB specifications affirms the leading role that the organization impacts for open source hardware and software development tools. We look forward to faster adoption of AIB as an open source chiplet interface.”  

About the CHIPS Alliance

The CHIPS Alliance is an organization which develops and hosts high-quality, open source hardware code (IP cores), interconnect IP (physical and logical protocols), and open source software development tools for design, verification, and more. The main aim is to provide a barrier-free collaborative environment, to lower the cost of developing IP and tools for hardware development. The CHIPS Alliance is hosted by the Linux Foundation. For more information, visit chipsalliance.org.

About the Linux Foundation

The Linux Foundation was founded in 2000 and has since become the world’s leading home for collaboration on open source software, open standards, open data, and open hardware. Today, the Foundation is supported by more than 1,000 members and its projects are critical to the world’s infrastructure, including Linux, Kubernetes, Node.js and more. The Linux Foundation focuses on employing best practices and addressing the needs of contributors, users, and solution providers to create sustainable models for open collaboration. For more information, visit linuxfoundation.org.

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CHIPS Alliance announces technical milestones, three new workgroups including Chisel and the 3rd Chisel Community Conference

By Announcement

SAN FRANCISCO, Nov. 7, 2019 — CHIPS Alliance, the leading consortium advancing common, open hardware for interfaces, processors and systems, today announced the creation of Interconnects, Rocket and Chisel workgroups. In addition, a November verification workshop in Munich and a Chisel conference in January will be held giving engineers an opportunity to learn about open source development efforts in CHIPS Alliance. Lastly, the CHIPS Alliance toolchain and cores workgroups have made contributions to open source development tools.

CHIPS Alliance is the project hosted by the Linux Foundation to foster a collaborative environment to accelerate the creation and deployment of open SoCs, peripherals and software tools for use in mobile, computing, consumer electronics, and Internet of Things (IoT) applications. The CHIPS Alliance project develops high-quality open source Register Transfer Level (RTL) code and software development tools relevant to the design of open source CPUs, RISC-V-based SoCs, and complex peripherals for Field Programmable Gate Arrays (FPGAs) and custom silicon. 

The Open Source Design Verification Workshop in Munich is being held on November 14th and 15th. CHIPS Alliance is hosting the third Chisel Community Conference to be held on January 29-30th in Milpitas, CA. Chisel is a hardware-construction language, hosted in Scala, and is used in both academia and industry to generate RTL for digital hardware. The Chisel community is joining CHIPS Alliance to further accelerate the development of open source hardware and software. Call for papers is open now.

CHIPS Alliance has also formed three new workgroups, Interconnects, Rocket and Chisel. The Interconnects group will further develop OmniXtendTM and TileLink. These groups will begin work imminently to make key contributions to open development tools and hardware. Go to www.chipsalliance.org to learn more or join a workgroup. In addition, the Cores and Toolchain workgroups have completed the following milestones

  • Created a portable SoC based on the SweRV CoreTM EH1 using FuseSoC
    • Includes debug port and Zephyr support
  • Verilator, the open-source simulator, is extended to add CMake and Python support for Cocotb
  • Verilator project for SystemVerilog kicked off 

“The rest of the developer team and I are very excited for Chisel to move to its new home in CHIPS Alliance. Now with open-source industry backing, Chisel is primed to continue growing its user base, adding new features, and stabilizing its infrastructure and ecosystem for industry applications.” – Adam Izraelevitz, PhD candidate at UC Berkeley and a lead developer of the Chisel ecosystem.

“We want to personally thank Olof Kindgren, Wilson Snyder and Stefan Wallentowitz for their key contribution to open source software development. These extraordinary individuals were vital to achieving these milestones. We look forward to further participation in CHIPS Alliance to facilitate the adoption of open architectures,” said Dr. Zvonimir Bandić, Chairman, CHIPS Alliance, and senior director of next-generation platforms architecture at Western Digital.

“Antmicro firmly believes in CHIPS Alliance’s vision of fully open tools and workflows as a foundation of an open ecosystem.”, said Michael Gielda, Chair of Marketing, CHIPS Alliance, VP Business Development at Antmicro, “Our work with open source simulation and verification, as well as production-grade SystemVerilog support in open source tooling relies on a collaborative environment where common milestones can be achieved faster.”

About the CHIPS Alliance

The CHIPS Alliance is an organization which develops and hosts high-quality, open source hardware code (IP cores), interconnect IP (physical and logical protocols), and open source software development tools for design, verification, and more. The main aim is to provide a barrier-free collaborative environment, to lower the cost of developing IP and tools for hardware development. The CHIPS Alliance is hosted by the Linux Foundation. For more information, visit chipsalliance.org.

About the Linux Foundation

The Linux Foundation was founded in 2000 and has since become the world’s leading home for collaboration on open source software, open standards, open data, and open hardware. Today, the Foundation is supported by more than 1,000 members and its projects are critical to the world’s infrastructure, including Linux, Kubernetes, Node.js and more. The Linux Foundation focuses on employing best practices and addressing the needs of contributors, users, and solution providers to create sustainable models for open collaboration. For more information, visit linuxfoundation.org.

CHIPS Alliance growth continues with new members and design workshop this November

By Announcement

SAN FRANCISCO, Oct. 15, 2019 /PRNewswire/ — CHIPS Alliance, the leading consortium advancing common, open hardware for interfaces, processors and systems, today announced Codasip GmbH and Munich University of Applied Science have joined the CHIPS Alliance. In addition, on November 14–15, CHIPS Alliance will be joining the university for a workshop on open source design verification.

CHIPS Alliance is a project hosted by the Linux Foundation to foster a collaborative environment to accelerate the creation and deployment of open SoCs, peripherals and software tools for use in mobile, computing, consumer electronics, and Internet of Things (IoT) applications. The CHIPS Alliance project develops high-quality open source Register Transfer Level (RTL) code relevant to the design of open source CPUs, RISC-V-based SoCs, and complex peripherals for Field Programmable Gate Arrays (FPGAs) and custom silicon.

Codasip is a leading supplier of configurable RISC-V® embedded processor IP. Codasip provides a portfolio of various RISC-V implementations along with a suite of processor developers tools to allow for rapid core customization, and will contribute to working groups on verification platforms and open cores.

“Codasip has years of processor development experience and has shown its dedication to open platforms by its contributions to open source compiler and compliance projects. We welcome their participation in the CHIPS Alliance to facilitate the adoption of open architectures,” said Zvonimir Bandić, senior director of next-generation platforms architecture at Western Digital and Chairman, CHIPS Alliance.

“Codasip is excited to join the CHIPS Alliance and support the community in its efforts to ease the path of adoption of RISC-V processors in leading-edge SOC applications,” said Karel Masařík, CEO of Codasip. “The CHIPS Alliance is the logical next step in providing chip designers more choices when it comes to processor architectures.”

Munich University of Applied Sciences aims to secure an outstanding position as a university of applied sciences. It recognizes the future demands of society and industry, and is changing with a critical yet open vision for current issues, such as the ongoing digitalization of all areas of life. The university focuses on continuous improvement of quality and on constant development in research, teaching, and continuing education.

“We strongly believe in open source silicon and design flows,” said Stefan Wallentowitz, professor for computer architecture at MUAS. “We look forward to improving open source verification tools together with innovative companies in that field.”

In cooperation with Munich University of Applied Science, the CHIPS Alliance is conducting an open source design verification workshop in Munich. The workshop invites contributions from industry, academia and hobbyists as talks or tutorials. Registration is open now for the November 14–15 event.

About Codasip

Codasip delivers leading-edge processor IP and high-level design tools, providing ASIC designers with all the advantages of the RISC-V open ISA, along with the unique ability to automatically optimize the processor IP. As a founding member of the RISC-V Foundation and a long-term supplier of LLVM and GNU-based processor solutions, Codasip is committed to open standards for embedded processors. Formed in 2006 and headquartered in Munich, Germany, Codasip currently has offices in the US and Europe, with representatives in Asia and Israel. For more information about our products and services, visit www.codasip.com.

About the CHIPS Alliance

The CHIPS Alliance is an organization which develops and hosts high-quality, open source hardware code (IP cores), interconnect IP (physical and logical protocols), and open source software development tools for design, verification, and more. The main aim is to provide a barrier-free collaborative environment, to lower the cost of developing IP and tools for hardware development. The CHIPS Alliance is hosted by the Linux Foundation. For more information, visit chipsalliance.org.

About the Linux Foundation

The Linux Foundation was founded in 2000 and has since become the world’s leading home for collaboration on open source software, open standards, open data, and open hardware. Today, the Foundation is supported by more than 1,000 members and its projects are critical to the world’s infrastructure, including Linux, Kubernetes, Node.js and more. The Linux Foundation focuses on employing best practices and addressing the needs of contributors, users, and solution providers to create sustainable models for open collaboration. For more information, visit linuxfoundation.org.

Media Contact

Chris Jones, VP of Marketing
E-mail: jones@codasip.com

CHIPS Alliance Builds Momentum and Community with Newest Members Imperas Software and Metrics

By Announcement

Imperas and Metrics joining CHIPS Alliance to help drive the verification of RISC-V Open ISA implementations

SAN FRANCISCO – June 18, 2019 – CHIPS Alliance, the leading consortium advancing common, open hardware for interfaces, processors and systems, today announced Imperas and Metrics are joining the organization and the Verification Working Group. Imperas is an independent provider of processor simulation technology and tools for virtual platforms and
analysis tools for multicore SoC software development. Metrics leads the cloud-based solutions for SoC designers with hardware simulation for both design management flexibility and on-demand capacity. The CHIPS Alliance welcomes Imperas and Metrics among its current members Antmicro, Esperanto Technologies, Google, SiFive, Western Digital.

CHIPS Alliance is a project hosted by the Linux Foundation to foster a collaborative environment to accelerate the creation and deployment of open SoCs, peripherals and software tools for use in mobile, computing, consumer electronics, and Internet of Things (IoT) applications. The CHIPS Alliance project hosts and curates high-quality open source Register Transfer Level (RTL) code relevant to the design of open source CPUs, RISC-V- based SoCs, and complex peripherals for Field Programmable Gate Arrays (FPGAs) and custom silicon.

Imperas provides reference processor models for verification of processors and SoC’s and will be contributing to the CHIPS Alliance working group on verification. Planned contributions will include enhanced interfaces and design flow methodologies to the riscvOVPsim ISS (Instruction Set Simulator) for RISC-V processor IP verification and compliance. riscvOVPsim is free and available for download on GitHub as part of the latest RISC-V compliance test suite and framework, available on GitHub at https://github.com/riscv/riscv-compliance

Metrics is the first cloud platform for ASIC and complex FPGA design verification. The company provides design teams with on-demand simulation resources, a modern continuous integration workflow, a pricing by-the-minute business model and unique development flexibility. Metrics develops innovative products powered by a cross-functional team that includes simulation technologists, IC design verification experts, and modern cloud software developers.

“Within the RISC-V community and ecosystem Imperas has made many contributions to customer and community projects and also released a free RISC-V reference simulator on GitHub, while Metrics has pioneered a cloud-based approach that enables infinite hardware simulation capacity that changes the nature of semiconductor verification use models,” said
Zvonimir Bandic, senior director of next-generation platforms architecture at Western Digital and Chairman, CHIPS Alliance. “With Imperas joining CHIPS Alliance we welcome their contributions within the verification task group to help the industry wide efforts to ensure quality IP is available to all adopters of RISC-V. Metrics’ contributions to verification
infrastructure will provide a modern approach to RISC-V cores, peripherals, and complex IP block development.”

“Imperas is pleased to join the CHIPS Alliance and support the continuing efforts to improve verification for all RISC-V implementers and SoC designers,” said Simon Davidmann, CEO of Imperas Software. “Open ISA’s are enabling new approaches and innovations in processor architectures that will require broad community support to address the verification challenges of next generation domain specific optimized devices.”

“Metrics was founded with an open platform philosophy that has allowed the company to form many valuable relationships that drive next-generation verification approaches,” said Doug Letcher, CEO, Metrics. “In joining CHIPS Alliance, we are excited to help and support industry wide collaborations for verification that are essential for the next generation
of devices.”

“CHIPS Alliance has seen a tremendous wave of interest and support since it was first announced just a few months ago,” said Ted Marena, Interim Director CHIPS Alliance. “We are pleased to welcome Imperas and Metrics as its latest members and both will be in attendance at the inaugural workshop on June 19, 2019 at Google at 111 W. Java Drive, Sunnyvale, Calif.”

The CHIPS Alliance community includes technology developers and contributors supported by a Board of Directors and a Technical Steering Committee. Its initial plans focus on establishing a curation process aimed at providing the FPGA and chip community access to high-quality, enterprise grade hardware.

About Imperas
Imperas is revolutionizing the development of embedded software and systems and is the leading provider of RISC-V processor models and virtual prototype solutions. Imperas, along with Open Virtual Platforms (OVP), promotes open source model availability for a spectrum of processors, IP vendors, CPU architectures, system IP and reference platform models of
processors and systems ranging from simple single core bare metal platforms to full heterogeneous multi-core systems booting SMP Linux. All models are available from Imperas at www.imperas.com and the Open Virtual Platforms (OVP) website.

About Metrics
Metrics, headquartered in Ottawa, Ontario, Canada, is the first true cloud-based platform for ASIC and complex FPGA Design Verification. The Metrics Platform provides an infinitely scalable design verification workflow together with advanced simulation technology, which reduces infrastructure waste and enables better engineering efficiency.https://metrics.ca/

About the Linux Foundation
Founded in 2000, the Linux Foundation is supported by more than 1,000 members and is the world’s leading home for collaboration on open source software, open standards, open data, and open hardware. Linux Foundation’s projects are critical to the world’s infrastructure, including Linux, Kubernetes, Node.js and more. The Linux Foundation’s
methodology focuses on leveraging best practices and addressing the needs of contributors, users, and solution providers to create sustainable models for open collaboration. For more information, please visit us at linuxfoundation.org.

The Linux Foundation has registered trademarks and uses trademarks. For a list of trademarks of the Linux Foundation, please visit our trademark usage page at https://www.linuxfoundaton.org/trademark-usage. Linux is a registered trademark of Linus Torvalds.

CHIPS Alliance to Reveal Project Details, Strategy and Roadmap at Inaugural Workshop Hosted at Google

By Announcement

SAN FRANCISCO –  May 7, 2019 – CHIPS Alliance, the leading consortium advancing common, open hardware for interfaces, processors and systems, today announced it is holding its inaugural workshop on June 19, 2019 at Google at 111 W. Java Drive, Sunnyvale, Calif.

Project details, strategy and roadmaps will be presented by member companies, and attendees will have an opportunity to propose Register Transfer Level (RTL) projects and development flow ideas. The workshop will focus on open source hardware, software tools, RTL development, design verification tools and related topics. The agenda and registration details are available at https://events.linuxfoundation.org/events/chips-alliance-workshop-2019

“This workshop at Google will kick off CHIPS Alliance hardware RTL development. The organization will discuss the planned projects, what is needed for accelerated open source hardware and key software tools. Attendees will see the potential of CHIPS Alliance and the vision for what we will deliver,” said Dr. Zvonimir Bandic, Western Digital and Chairman of the CHIPS Alliance Foundation.

“Workshop attendees will learn more about our organization and the open source hardware, verification flows/tools and software we will be developing. Attendees will also have an opportunity to suggest projects and meet with CHIPS Alliance members and the Board of Directors. We look forward to answering questions, discussing ideas and sharing the aspirations of the group,” said Dr. Richard Ho, Google and Board member of the CHIPS Alliance Foundation.

CHIPS Alliance members include Antmicro, Esperanto Technologies, Google, SiFive and Western Digital. The Alliance is a collaborative forum designed to accelerate the creation and deployment of more efficient and flexible CPUs, SoCs and complex peripherals for FPGAs and custom silicon. It is supported by a Board of Directors and a Technical Steering Committee.

CHIPS Alliance Inaugural Workshop Agenda

  • 9:00   Introduction to CHIPS Alliance (Zvonimir Bandic)
  • 9:15   Why open source hardware unlocks innovation (Martin Fink)
  • 9:40      Federation: An Open-Source Chip Design Workflow  (Yunsup Lee)
  • 10:05    Collaborative end to end Design Verification Flow  (Richard Ho)
  • 10:30  Break
  • 11:00  RISC-V SweRV Core contribution (Zvonimir Bandic)
  • 11:20  Open Source Tools: cocotb and Verilator support  (Michael Gielda)
  • 11:40  Verilator and Test Bench Environment roadmap (Wilson Snyder)
  • 12:00  Lunch
  • 1:00    A natural fit, RISC-V with CHIPS Alliance (Naveed Sherwani)
  • 1:25    BooM v2 coordination with UC Berkeley (Dave Ditzel)
  • 1:50    Audience Participation – What RTL IP do you want to be designed?
  • 2:30   Break
  • 3:00   Blue Cheetah Framework for Rapid IP Design (Krishna Settaluri)
  • 3:25   FuseSoC support for SweRV (Olof Kindgren)
  • 3:40   Chisel and FIRRTL  (Yunsup Lee)
  • 4:00   Why join CHIPS Alliance? (Ted Marena)

 

About The Linux Foundation
Founded in 2000, the Linux Foundation is supported by more than 1,000 members and is the world’s leading home for collaboration on open source software, open standards, open data, and open hardware. Linux Foundation’s projects are critical to the world’s infrastructure, including Linux, Kubernetes, Node.js and more. The Linux Foundation’s methodology focuses on leveraging best practices and addressing the needs of contributors, users, and solution providers to create sustainable models for open collaboration. For more information, please visit us at linuxfoundation.org.

 

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The Linux Foundation has registered trademarks and uses trademarks. For a list of trademarks of the Linux Foundation, please visit our trademark usage page at https://www.linuxfoundaton.org/trademark-usage. Linux is a registered trademark of Linus Torvalds.