#verilatorJuly 22, 2026Initial implementation of four-state logic in the open source Verilator RTL simulator
#announcement #dac #eventsJuly 21, 2026CHIPS Alliance at the DAC 2026 Open Source EDA Birds-of-a-Feather Session
#Developer SpotlightJune 29, 2026CHIPS Alliance Developer Spotlight: Stefano Righi, Chief Security Architect, AMI
#project-update #caliptra #veerJune 29, 2026Dual-core Lockstep in the VeeR EL2 RISC-V core for safety-critical applications and side-channel access mitigation in Caliptra RoT
#systemverilog #veribleMarch 30, 2026CHIPS Alliance launches the SV Tools Project for open source development of SystemVerilog/UVM codebases
#topwrap #risc-v #asic-design #guineveer #veerMarch 18, 2026Designing Modular and Reusable RISC-V SoCs with Topwrap and Guineveer
#caliptra #systemverilog #openprot #f4pgaFebruary 5, 2026CHIPS Alliance - Our Vision and Priorities for 2026
#caliptra #chisel #openprot #veerJanuary 15, 2026CHIPS Alliance 2025- A Year of Breakthroughs in Open Silicon and the Road Ahead
