Blog

January 30, 2025

New revision of Data Center RDIMM DDR5 Tester

January 21, 2025

Constrained randomization in Verilator

January 9, 2025

Caliptra - Support for VeeR EL2 with User Mode and Physical Memory Protection in Tock embedded OS

December 20, 2024

Topwrap – open source toolkit for modular, parameterizable digital logic design

October 13, 2024

Caliptra @ OCP Global Summit 2024

June 21, 2024

Initial assertion control support in Verilator

May 24, 2024

Speeding Up OpenROAD For Fast Design Feedback

March 25, 2024

Adding Physical Memory Protection to the VeeR EL2 RISC-V Core

March 18, 2024

Analyze Verilator processes and ASTs with the astsee suite

March 11, 2024

Versatile SO-DIMM (LP)DDR5 Rowhammer testing platform

November 8, 2023

Initial Open Source Support for UVM Testbenches in Verilator

September 29, 2023

Verilator Model Generation Performance Improvements and Initial Multithreaded Verilation Support