CHIPS Alliance’s general manager Rob Mains joined Amelia Dalton at EE Journal’s FishFry podcast for a lively discussion about how we’re working to make chip design more accessible. Rob discussed CHIPS Alliance’s work with RISC-V International to develop a new unified memory standard, along with our work to accelerate the design of open source chipsets with the AIB 2.0 specification. The conversation also touched on our efforts to provide better support for SystemVerilog using open source tools and to create a dynamic stratified scheduler implementation in Verilator.
Check out the podcast here. The conversation with Rob starts at 7:03.