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rmains

F4PGA open source flow gets a new Python-based build system and CLI tool

By F4PGA

One of the most recent projects developed within the workgroup is the unified f4pga CLI tool. In the broader context of our continuous efforts to make the FPGA space more unified and flexible, creating the f4pga CLI tool was a logical next step – it allowed us to wrap the underlying tools into a single CLI, making the F4PGA toolchain a more complete flow. The currently supported architectures are AMD’s (former Xilinx) 7 Series, Lattice’s iCE40 and QuickLogic’s EOS S3. Details are here:

https://antmicro.com/blog/2022/09/f4pga-new-build-system-and-cli-tool

Skywater

By Blog

It’s great to learn that Google  announced the expansion of its partnership with SkyWater Technology. They are working together to release an open source process design kit (PDK) for SKY90-FD, SkyWater’s commercial 90nm fully depleted silicon on insulator (FDSOI) CMOS process technology. SKY90-FD is based on MIT Lincoln Laboratory’s 90 nm commercial FDSOI technology, and enables designers to create complex integrated circuits for a diverse range of applications.

You can read more @ https://opensource.googleblog.com/2022/07/SkyWater-and-Google-expand-open-source-program-to-new-90nm-technology.html

Catch us at DAC 59 in San Francisco starting July 11

By Announcement

Come learn about open source hardware and CHIPS Alliance at next week’s 59th Design Automation Conference in San Francisco. We will be at kiosk 2344 in the RISC-V pavilion. You can also here out talk at 12:30 Monday in the Open Source Central Theatre (booth 2338). We are also in a DAC Pavilion Panel: Is Democratization of Chip Design Already Happening? at 2:30 on Monday. Look forward to an exciting day in SF!

Enhanced System Verilog Support for Yosys via Antmicro plug-in

By Blog

CHIPS Alliance is pleased to see the announcement by Antmicro for its development and contribution to the open source hardware community to provide a easy to use plug-in for any version of Yosys to allow import of System Verilog based designs. This development is made possible by the underlying utilization of the Unified Hardware Data Model (UHDM), a key open source data representation upon which EDA applications can be built. Details can be seen here from Antmicro: https://antmicro.com/blog/2022/02/simplifying-open-source-sv-synthesis-with-the-yosys-uhdm-plugin/