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Open Source Process Design Kit from Google, SkyWater Technologies and Partners Released

By Blog

This post was originally published at Antmicro.

The ASIC design and manufacturing flow has for a long time been dominated by proprietary tools and processes. The growing complexity of chip-building has been reinforcing the claim that “hardware is too hard to be open source”, as the cost and time needed to build an ASIC have kept small, more agile, software-oriented teams and individuals away from the hardware domain. Thus, ASICs have not been able to benefit from the enthusiasm and collaboration which have been fuelling software development for decades now. Thanks to the continued effort of many entities which Antmicro is very proud to be among, this is now changing quickly.

RISC-V: Openness-driven innovation

The first shift in the walled garden, proprietary chips design landscape came with the creation of the RISC-V Foundation in 2015 centered around the open source RISC-V ISA. Antmicro has been on board as a Platinum Founding Member of the Foundation (now, several hundred members strong, transitioning into a Swiss-based entity called RISC-V International) since the very beginning, as it reflected our belief that an open source approach can – and is bound to, eventually – revolutionize all areas of computing, even the less obvious ones.

RISC-V proved ASIC design can be a collaborative process, with players big and small working together to compliment each other’s strengths not only in developing the ISA but also many of the tools needed to make it practically useful. For example, Microsemi worked with SiFive to provide the SoC complex at the heart of their new and exciting PolarFire FPGA SoC, and then turned to Antmicro to provide a simulation environment – using our open source Renode Framework – to make development possible before the SoC hits the market later this year. The OpenTitan project, driven by key RISC-V adopters Google and Western Digital together with the UK not-for-profit lowRISC, strives to build a more transparent, trustworthy, high-quality reference design and integration guidelines for silicon Root of Trust chips. Such examples abound in the RISC-V world, but the un-core, design tools, verification and other parts of the ecosystem have mostly remained closed.


Established in 2019, CHIPS Alliance takes the open, collaborative aspect of RISC-V even further. CHIPS wants to generate and integrate fully open source, high quality IP and tooling for ASIC design; the organization extends beyond cores and specifications, and acknowledges the importance not only of the result but the process itself; thus, the aim is to make both ASICs and the ASIC design processes open source all the way. Why? Again, a lesson learned from software: if you open up to collaboration, adaptation and change on all levels, the long-term results will be surprisingly good.

CHIPS has been home to such important projects as the Chisel HDL, the Rocket core generator and related tools, the SweRV cores or AIB interconnect. There is work under way to enable fully open source SystemVerilog/UVM support in tools like Verilator and Yosys (with some milestones like fully open source linting, formatting or synthesis of SystemVerilog code already accomplished), opening the door to more open source collaboration around design verification which constitutes the highest cost in modern chip design.

Also in the tools area, the very ambitious OpenROAD project, also a CHIPS member, is a DARPA-backed activity aiming to create a fully open source, quick, automated digital design flow. If you want to see how open source, automated chip design might look like in the future, see OpenROAD’s excellent ChipKit tutorial from ISCA 2020.

Aggregating those activities a vastly different landscape begins to emerge, one where chip design can be innovated upon on various levels, and teams can go back and forth between hardware and software optimizations for new use cases such as machine learning without NDAs and costly licences. But – until now – there was one element notably missing.

First ever open source PDK

We are excited to announce Antmicro’s participation in yet another historic first in the area of semiconductor process technology. In a project led by Google and SkyWater Technology, and in collaboration with partners including Antmicro, Blue Cheetah, efabless and numerous Universities, an open source SkyWater PDK (Process Design Kit) for the 130 nm MOSFET fabrication process, along with related sources, is being made available. This development greatly lowers the cost of entry into chip manufacturing and paves the way for even more exciting collaborations to happen in the open source silicon domain.

For some background, a PDK is a set of data files and tools used to model a specific process in a given foundry used with EDA (Electronic Design Automation) tools in the chip design flow. PDKs traditionally have been closed – to the point where some would say it’s impossible to make them open! This collaboration, where Antmicro worked together with Google and efabless to convert the PDK data for the public release, is an important step towards truly open source chips. The 130nm PDK process is a mature technology that is useful for a range of applications, especially in the area of microcontroller development and research as well as mixed signal embedded designs and other use cases which combine digital and analog circuits. The SKY130 technology stack consists of:

  • 1 level of local interconnect
  • 5 levels of metal
  • Inductor-capable
  • High sheet rho poly resistor
  • Optional MiM capacitors
  • Includes SONOS shrunken cell
  • Supports 10V regulated supply
  • HV extended-drain NMOS and PMOS

SkyWater is an American technology foundry accredited by the US Department of Defense, which offers custom integrated circuit design and manufacturing services. It is predicted that the launch of the open source SKY130 process node will be followed by other, more advanced nodes, ultimately enabling more advanced processor applications, including ones that are Linux-capable.

The inaugural talk by Tim Ansell

On Tuesday, June 30 at 16:00 GMT, Google’s Tim Ansell will give a talk at the FOSSi Dial-up meeting, presenting a thorough overview of the technical details of the PDK, as well as outlining the project’s goals and its roadmap. The event will be livestreamed on YouTube and will be followed by a Q&A session, so tune in to find out more about this historic step towards an open, accessible and collaborative chip-making process.

Semiconductor Engineering: About The SweRV Core EH2

By Blog

In mid-May, CHIPS Alliance announced the open sourcing of the SweRV Core EH2 and SweRV Core EL2 designed by Western Digital. These cores, as well as the earlier EH1, are now supported by Codasip’s SweRV Core Support Package which provides all of the components necessary to design, implement, test, and write software for a SweRV Core-based system-on-chip. But what is SweRV Core EH2?

The SweRV Core EH1 was the first to be released through CHIPS Alliance and was a core aimed at high-end embedded applications including Western Digital’s flash controllers and SSDs. The core is a dual issue, superscalar, high-performance core with 9 pipeline stages. The EH2 is an exciting further development aimed at delivering even more performance for IoT, artificial intelligence and data-intensive embedded applications.

To read more, please check out the article at Semiconductor Engineering written by Roddy Urquhart at Codasip:

QuickLogic Announces Open Reconfigurable Computing Initiative

By Blog

Originally issued by QuickLogic, the following press release announces the QORC initiative including the world’s first vendor-supported open FPGA toolchain using SymbiFlow, and describes the contribution of CHIPS Alliance members Antmicro and Google.

  • QuickLogic Open Reconfigurable Computing (QORC) initiative, developed by Antmicro in collaboration with QuickLogic and Google, broadens access to company’s FPGA technology and eFPGA IP for all embedded systems developers
  • First Programmable Logic Company to Embrace Open Source FPGA Development Tools

San Jose, CA – June 16, 2020 – QuickLogic Corporation (NASDAQ: QUIK), a developer of ultra-low power multi-core voice-enabled SoCs, embedded FPGA IP, and Endpoint AI solutions, today announced its ground breaking QORC (QuickLogic Open Reconfigurable Computing) initiative, making it the first programmable logic vendor to actively embrace a fully open source suite of development tools for its FPGA devices and eFPGA technology. This initiative engenders the emerging trend toward open source tooling, significantly broadens access to the company’s products, and enables both hardware and software developers with tools supported by both the user community and QuickLogic.The company’s initial open source development tools, developed by Antmicro in collaboration with QuickLogic and Google, include complete support for its EOS S3 low power voice and sensor processing MCU with embedded FPGA, and its PolarPro 3E discrete FPGA family. Support for additional QuickLogic products, including QuickAI and support for its eFPGA IP offering will be added over the next few months.

EOS S3 Open Source Development Tools:

  • FPGA Development Flow: SymbiFlow – Open source tools for the optimization and automation of the FPGA design flow, from Verilog to bitstream generation. These tools enable innovation by making FPGAs more accessible to a broader community.
  • SoC Emulation: Renode – Antmicro’s Renode is an open source simulation framework for rapid prototyping, development and testing of multi-node systems. Utilizing Renode gives developers the flexibility to fully evaluate multiple development board applications.
  • Zephyr Real Time Operating System (RTOS) – The Zephyr RTOS is an open source, vendor-neutral, compact, real-time operating system running on the Arm Cortex® M4F for connected, resource-constrained and embedded devices in applications that require security and safety.
  • QuickFeather Development Kit – A small form factor, 100% open source hardware development kit ideal for the next generation of low-power Machine Learning (ML) capable IoT devices.

Traditionally, programmable logic vendors offered and supported only proprietary synthesis, place and route tools. Open source tools were relegated to hobbyists, academics, and independent consultants. However, the electronics industry is starting to see a shift toward open sourced hardware and software as it provides flexibility, vendor and community support, longevity, and adaptability to each engineer’s design flow. Google and Antmicro have been noteworthy influencers in this market, increasing the breadth of supported architectures and quality of results for the open source tools. They are now not only viable but desirable for the majority of the development community, including design teams at many of the industry’s largest companies.

“QORC is QuickLogic’s initiative to embrace the rapidly growing open source FPGA tooling ecosystem, inspiring engineers to collaborate on the creation of exciting and innovative products,” said Brian Faith, QuickLogic’s president and CEO. “We believe that the wide adoption of open source tools represents a paradigm shift for the industry, and we’re proud to be at the leading edge.”

“With its open source-centered approach, Antmicro has been moving the technological frontier, building whole ecosystems of non-proprietary solutions and overcoming the limitations inherent in closed technologies,” said Michael Gielda, Antmicro’s VP of Business Development. “We’ve been excited to participate in this historical first from QuickLogic, by contributing our expertise in software, hardware and tools to implement the necessary SymbiFlow, Renode and Zephyr support for their hardware platform – broadening their reach within the developer community.”


SymbiFlow FPGA, Renode SoC Emulation, and Zephyr RTOS support are available now for QuickLogic’s EOS S3 voice and sensor processing platform and PolarPro 3E FPGA products, as well as the new QuickFeather Development Kit. Support for QuickLogic’s embedded FPGA technology will be added later this year. To learn more, please visit

About QuickLogic

QuickLogic Corporation (NASDAQ: QUIK) is a fabless semiconductor company that develops low power, multi-core semiconductor platforms and Intellectual Property (IP) for Artificial Intelligence (AI), voice and sensor processing. The solutions include embedded FPGA IP (eFPGA) for hardware acceleration and pre-processing, and heterogeneous multi-core SoCs that integrate eFPGA with other processors and peripherals. The Analytics Toolkit from our recently acquired wholly-owned subsidiary, SensiML Corporation, completes the end-to-end solution with accurate sensor algorithms using AI technology. The full range of platforms, software tools and eFPGA IP enables the practical and efficient adoption of AI, voice, and sensor processing across mobile, wearable, hearable, consumer, industrial, edge and endpoint IoT. For more information, visit and

QuickLogic and logo are registered trademarks and EOS and SensiML are trademarks of QuickLogic. All other trademarks are the property of their respective holders and should be treated as such.

Press Contact:

Andrea Vedanayagam
Veda Communications

A Look Back at the CHIPS Alliance’s Incredible Growth

By Blog

It’s been just over a year since the CHIPS Alliance was founded with the mission of making open source hardware development more accessible to companies, universities and individuals. We’re working to bring the dynamics of the hugely successful open source software development model into ASIC design, building on the groundwork set by the RISC-V community. Progress over the past year is detailed in our Annual Report

 CHIPS Alliance is focused on expanding on this open hardware vision by:

  • Targeting other parts of ASICs beyond the CPU core, gradually open sourcing all IPs that go into a SoC, both analog and digital.
  • Open sourcing the tools needed to work with ASICs, making it possible to design innovative solutions without a massive upfront investment.
  • Providing real, battle-proven reference implementations and project infrastructure to ensure the continued success of the projects we govern and support.

 With these three pillars guiding our efforts, we believe that the CHIPS Alliance will enable truly open hardware to flourish for the first time. The CHIPS Alliance has already made incredible progress so far. We have achieved a number of important technical milestones, including announcing newly enhanced SweRV Cores – EH2 and EL2 – and releasing the Advanced Interface Bus (AIB) specification and reference implementations by one of the CHIPS Alliance’s newest members, Intel. These technical accomplishments are making it easier for engineers to design innovative embedded applications for the latest computing requirements.

We’re also excited by the significant community interest in the work we’re doing. Hundreds of people from around the world have attended CHIPS Alliance events over the past year, both in-person and online, and our working groups are running full steam ahead. Check out our Annual Report to learn more about the CHIPS Alliance’s news and activities, and stay up to date by following us on Twitter and LinkedIn.

CHIPS Alliance’s Newly Enhanced SweRV Cores Available to All for Free

By Announcement

CHIPS Alliance to host online event to help community innovating with SweRV Core EH2 and EL2 Solutions

SAN FRANCISCO, May 14, 2020 – CHIPS Alliance, the leading consortium advancing common and open hardware for interfaces, processors and systems, today announced new enhancements to the SweRV Core™ EH2 and SweRV Core EL2, developed for the open-source community by Western Digital. Since the introduction of the cores earlier this year, the CHIPS Alliance has worked with its community to exhaustedly validate the cores through a transparent and rigorous process, as well as incorporate a variety of new updates.

The SweRV Core EH2, the world’s first dual-threaded, commercial, embedded RISC-V core, is designed for embedded devices supporting data-intensive edge, artificial intelligence (AI) and Internet of Things (IoT) applications. SweRV Core EL2 is an ultra-small, ultra-low-power RISC-V core optimized for applications such as state-machine sequencers and waveform generators. The newly updated cores are now available to everyone for free.

CHIPS Alliance will host an online event to discuss the SweRV Core EH2 and EL2, along with the available software support and solutions for programmers on May 20, 2020 at 5:30 p.m. PT. The event will feature talks from representatives of Antmicro, CHIPS Alliance, Codasip, Metrics and Western Digital.

“Our work to help bring the newly enhanced SweRV Core EL2 and EH2 to the open hardware community demonstrates key progress towards our goal of accelerating RISC-V innovation. We’ve already seen significant industry interest in the SweRV Core EH1 and are pleased to offer two compelling additional options to engineers designing IoT, consumer, mobile and other embedded applications,” said Dr. Zvonimir Bandić, Chairman, CHIPS Alliance.

To register for the CHIPS Alliance virtual event on May 20, please visit:

To learn more about the SweRV Cores, please visit:

About the CHIPS Alliance

The CHIPS Alliance is an organization which develops and hosts high-quality, open source hardware code (IP cores), interconnect IP (physical and logical protocols), and open source software development tools for design, verification, and more. The main aim is to provide a barrier-free collaborative environment, to lower the cost of developing IP and tools for hardware development. The CHIPS Alliance is hosted by the Linux Foundation. For more information, visit

About the Linux Foundation

The Linux Foundation was founded in 2000 and has since become the world’s leading home for collaboration on open source software, open standards, open data, and open hardware. Today, the Foundation is supported by more than 1,000 members and its projects are critical to the world’s infrastructure, including Linux, Kubernetes, Node.js and more. The Linux Foundation focuses on employing best practices and addressing the needs of contributors, users, and solution providers to create sustainable models for open collaboration. For more information, visit


SystemVerilog Linting and Formatting with FuseSoC – Verible Integration

By Blog

This post was originally published at Antmicro.

Although new ASIC design methodologies and tools such as Chisel are on the rise, most ASIC projects still use SystemVerilog, the support of which in open source tools has traditionally lagged behind. This is unfortunate, as using proprietary alternatives with the CI systems of open source projects is neither scalable due to licensing costs and restrictions nor simple due to the need for license management and obfuscation.

Antmicro, Google and the CHIPS Alliance, which we are members of, have been working together with the lowRISC project to address this issue by implementing relevant tools and useful integrations in the open source domain. One large milestone on this route is Verible, an open source Flex/YACC SystemVerilog parser, linter and formatter recently open sourced by our partner and customer, Google.

Among other developments in that space, Antmicro has been helping to make Verible support some SystemVerilog features required for working with practical use cases, such as lowRISC’s ibex, a 32-bit RISC-V core used in the open source security project, OpenTitan. But to generate adoption, ease of use is just as important as features, which is why Verible was recently exposed to a wider audience by integrating it with FuseSoC.

One of the main advantages of an open source linter/formatter is how easy it is to integrate it with existing workflows of open source projects. As it happens, many open source FPGA/ASIC projects, including OpenTitan, are managed with FuseSoC, an open source tooling and IP package manager (from our fellow FOSSi veteran Olof Kindgren) which we also use and support. Thanks to the integration of Verible with FuseSoC, linting and formatting automation becomes much easier.

Below you will find a simple example and explanation of how to use the integration The example contains an accompanying CI setup which you can mimic in your own project.


We will use the following example repository to explain the usage of Verible with FuseSoC.
We will show how to build Verible binaries, download ibex – a small 32 bit RISC-V CPU core – and run FuseSoC to perform linting/formatting using Verible.


Install the prerequisites (tested on Ubuntu 18.04):

sudo apt update
sudo apt install cmake ninja-build wget python3 python3-pip python3-setuptools make tar git
sudo pip3 install fusesoc

Building Verible

Verible can be built using the Bazel build system.
Bazel is not available in the debian/ubuntu apt repositories. To install Bazel you should add Bazel’s apt repository:

curl | sudo apt-key add -
echo "deb [arch=amd64] stable jdk1.8" | sudo tee /etc/apt/sources.list.d/bazel.list
sudo apt update && sudo apt install bazel

To build Verible, a C++11 compatible compiler is required. After the installation of bazel, Verible can be built and installed:

git clone
cd Verible
bazel build -c opt //...
bazel run :install -c opt -- `pwd`/../Verible_bin
export PATH=`pwd`/../Verible_bin/:$PATH

Alternatively, you can download pre-built Verible binaries from the Verible release page. Refer to the Verible documentation and Bazel installation instructions for more details.

Running Verible tools with FuseSoC

FuseSoC uses tool backends available in edalize, which is another workflow automation project from the same author that we contribute to regularly. In order to use the Verible tools with FuseSoC you need to define a tool section in the FuseSoC core target file. Ibex already includes the integration, so you can use its ibex_core.core file as an example.

Verible linter with FuseSoC on ibex

To perform linting in ibex_core, use:

git clone
cd ibex
#add Verible lint rules
sed -i '132i\          - "-generate-label"\n          - "-unpacked-dimensions-range-ordering"\n          - "-explicit-parameter-storage-type"\n          - "-line-length"\n          - "-module-filename"\n          - "-no-trailing-spaces"\n          - "-undersized-binary-literal"\n          - "-struct-union-name-style"\n          - "-case-missing-default"\n          - "-explicit-task-lifetime"\n          - "-explicit-function-lifetime"' ibex_core.core

fusesoc --cores-root. run --target=lint --tool=veriblelint lowrisc:ibex:ibex_core:0.1

Verible formatter with FuseSoC on ibex

To format the ibex_core with Verible:

#add Veribleformat rules
sed -i '154i\          - "--max_search_states"\n          - "10000000"' ibex_core.core
fusesoc --cores-root . run --target=format --no-export lowrisc:ibex:ibex_core:0.1

The demo also shows how the Verible linter can be incorporated into CI pipelines for automatic detection of lint errors. To demonstrate that, a Pull Request containing an intentional lint error has been opened. An automatically executed CI pipeline was able to detect the issues with the code and inform the developers about the failed build status. The output of the lint command can provide useful information about a possible cause of the error. Early detection of lint errors can reduce the number of bugs and improve the overall code quality. Using a linter can accelerate development and reduce costs by finding errors at an early stage of the process. Moreover, incorporating the Verible formatter in CI can also ensure that incoming contributions automatically employ the project’s coding style.

More detailed instructions regarding building and using Verible with FuseSoC can be found in the README file located in the demo repository.

If you are involved in FPGA and ASIC development and want your project to be portable, modular and harness other benefits of a software-driven, open-source-based approach, Antmicro is there to help. As a key service provider in both RISC-V Foundation and CHIPS Alliance, we have lots of readily available SoC building blocks, tools and capabilities to assist you in developing your next product or platform.