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The CHIPS Alliance Workshop: 10 Talks From Industry Leaders, All For Free

By Blog

Mark your calendars! The CHIPS Alliance Workshop is coming up on Thursday, Sept. 17 from 11 a.m. to 2 p.m. PT. This free, virtual event will feature talks from industry leaders including Antmicro, Efabless, Google, Intel, Mentor, Metrics, OpenROAD, QuickLogic, SiFive, UC Berkeley and Western Digital.  

The CHIPS Alliance Workshop will fit 10 sessions into three hours for a jam-packed event covering a range of interesting topics in the open source community. You’ll hear about open source ASICs, chiplets, FPGAs and SoCs, in addition to open source design verification, FPGA tooling, machine learning accelerators and more. Read on for additional details, and make sure to register before it’s too late.

Check out the schedule below to learn more about what the sessions will cover:

  • 11:00 a.m. PT: Keynote Kick-Off – CHIPS Alliance
    • Brief welcome
  • 11:05 a.m. PT: Open Design Verification – Tao Liu, Google
    • Open source design verification is a key enabler for more collaborative flows in ASIC development. The RISC-V DV framework, based on an open source instruction set generator developed by Google, is enabling end-to-end verification flows for RISC-V CPUs.  The generator supports all RISC-V ISA extensions, and can be configured to generate highly random tests for various RISC-V processors. This talk will cover the fundamentals of the flow and recent developments including Bit-manipulation extension, Vector extension, multi-cores verification, functional coverage model, python based random instruction generator etc.  Learn more about the technology and its latest developments in Tao Liu’s talk. 
  • 11:25 a.m. PT: Enabling Fully Open Source And Continuous Integration-Driven Flows in ASIC and FPGA Development – Michael Gielda, Antmicro
    • ASIC and FPGA development is making rapid strides towards adopting fully open source, software-oriented approaches where large-scale collaboration and CI are possible. The developments include new frameworks such as UHDM and sv-tests aimed at improving SystemVerilog support in linting, formatting, synthesis and simulation, ongoing work in Verilator towards providing UVM support for open source verification, advances in the open source SymbiFlow toolchain which opens up FPGAs and ASIC prototyping to more software-oriented experimentation and collaboration. We also have the OpenROAD flow and SkyWater PDK tackling end-to-end open source ASIC design, and general progress in the open IP ecosystem – including new and exciting RISC-V and OpenPOWER cores – energizing the community. In this talk, Michael Gielda, VP Business Development at Antmicro, will highlight recent developments and explain the vision for open source chips that Antmicro and the CHIPS Alliance are spearheading.
  • 11:45 a.m. PT: The Emergence of the Open-Source AIB Chiplet Ecosystem – David Kehlet, Intel
    • The AIB chiplet ecosystem has built and powered on ten chiplets across seven process nodes, leveraging three different foundries, and contributing to two different product families.  Among the chiplet functions are AI acceleration, high-speed transceivers, optical interfaces, and high-speed ADCs/DACs.  The demand for AIB-enabled chiplets has spurred the release of an automated AIB PHY generator tool, which will help speed the next generation of AIB adopters to complete their projects.  Dave Kehlet, Research Scientist at Intel, will cover these topics, the new release of the AIB 2.0 specification with even higher bandwidth and lower power, and consideration of future layers needed as open source.
  • 12:05 p.m. PT: Chipyard: Design of customized open-source RISC-V SoCs – Borivoje Nikolic, UC Berkeley
    • Chipyard is an integrated SoC design, simulation and implementation environment for specialized compute systems. Chipyard includes configurable, composable, open-source, generator-based blocks that can be used in multiple stages of the hardware development flow, while maintaining design intent and integration consistency.  Chipyard is built around the open-source RocketChip generator, and targets cloud FPGA implementation and rapid ASIC implementation, allowing for continuous validation of physically realizable customized systems.
  • 12:25 p.m. PT: SweRV and OmniXtend Milestones – Zvonimir Bandic, Western Digital
    • The Open Source RISC-V SweRV Cores have been increasingly adopted by organizations who prioritize a validated, production worthy core. The latest updates on the first commercial dual threaded, embedded SweRV EH2 will be highlighted. This talk will discuss progress on the open cache coherent memory fabric, OmniXtend. The breakthrough architecture uses low cost Ethernet to connect memory to hosts. OmniXtend frees main memory from the CPU and enable next generation memory centric architectures to become a reality. 
  • 12:45 p.m. PT: Chisel & FIRRTL for next-generation SoC designs – Jack Koenig, SiFive
    • The Chisel Working Group is dedicated to improving the productivity of digital design and verification to enable next-generation SoC designs based on open-source tools. Its namesake project, Chisel HDL, is a domain-specific language embedded in Scala that provides designers with modern programming techniques like object orientation, functional programming, parameterized types, and type inference. CWG also includes FIRRTL, the hardware compiler framework that enables decoupling design from implementation via target specialization and custom transformations. In this talk, you’ll learn about the exciting improvements to the various projects, as well as the adoption of formal governance.
  • 1:05 p.m. PT: Open ML Accelerator – Anoop Saha, Mentor
    • High Level Design or High Level Synthesis (HLS) helps users to design hardware at a higher level of abstraction and consequently, improve productivity and reduce costs. This methodology has gained traction in the design of custom application specific accelerators for machine learning. In this talk, Mentor’s Anoop Saha will go over the HLS ecosystem and the open source HLS components that help in building an accelerator. This ecosystem provides resources from IP libraries to full toolkits with real working designs.
  • 1:25 p.m. PT: Cloud Based Verification of RISC-V Processors – Dan Ganousis, Metrics
    • Open-source ISAs such as RISC-V allow users to modify/optimize processor IP for their SW applications. With that benefit, however, comes the responsibility of the user to fully verify the modified processor IP. Many ASIC design groups do not have the requisite processor verification skills and simulation capacity and have realized delayed schedules and budget overruns. Metrics CloudSim provides a simple and economical verification solution in the Cloud that provides scalable computing, elastic storage, and a SaaS business model.
  • 1:35 p.m. PT: OpenROAD open RTL-to-GDS update – Andrew Kahng, OpenROAD/UCSD, and Mohamed Kassem, Efabless 
    • The OpenROAD project seeks to develop an open-source RTL-to-GDS tool that generates manufacturable layout from a given hardware description in 24 hours,  with no human in the loop. By reducing cost, expertise and schedule barriers to hardware design, OpenROAD enables greater access to ASIC implementation and accelerates system innovation in hardware. This talk will give an update on OpenROAD’s status and near-term outlook. The OpenROAD tool is integrated around  an open-source, commercial-quality database and timing engine. A SkyWater 130nm tapeout was made by efabless.com in May, and DRC-clean layout generation in GLOBALFOUNDRIES 12nm was achieved in July.  Efabless will describe the “OpenLANE” flow that integrates much of OpenROAD’s tooling, and the striVe family of SoCs being taped out on SKY130. 
  • 1:50 p.m. PT: Open Source FPGA Tooling, Our Journey from Resistance to Adoption – Brian Faith, QuickLogic
    • Since the inception of the Programmable Logic industry, the vendor-supported FPGA development tools have been proprietary and closed source. Initially this was simply because that is the way things were done – there were no open standards. But over time, keeping them closed and proprietary enabled a level of influence and control over users. If a designer liked your software, they tended not to change, and that implicitly makes your user base captive.  Open source FPGA tools have been around for a long time, being used primarily by hobbyists and in academia. However, over the past few years, an increasing number of new developers with software backgrounds are gravitating towards open source FPGA development tools.  With companies like Google and Antmicro, as well as several universities, making significant contributions to them, these tools are only going to keep getting better.  In this talk, Brian Faith, CEO of QuickLogic, will share their journey from resistance to adoption, how they decided to take the leap into open source FPGA tooling, becoming the 1st Programmable Logic company to do so.
  • 2:00 p.m. PT: Summary Wrap-Up

 

For more information about the CHIPS Alliance and our activities over the past year, check out our 2020 Annual Report and our recent news. We look forward to seeing you at the Workshop! 

Efabless Joins CHIPS Alliance to Accelerate the Growth of the Open Source Chip Ecosystem

By Announcement

Efabless to give a talk on the OpenROAD project at the CHIPS Alliance Workshop on Sept. 17

SAN FRANCISCO, Sept. 15, 2020 – CHIPS Alliance, the leading consortium advancing common and open hardware for interfaces, processors and systems, today welcomed Efabless, a crowdsourcing design platform for custom silicon, as its latest member. Efabless is already an active participant in several open source initiatives that the CHIPS Alliance is involved in, including the OpenROAD project and the Open Source Shuttle Program.

“The mission of the CHIPS Alliance to democratize silicon design nicely aligns with our focus on changing how chip design is done forever. Our platform is essentially an ecosystem-in-a-box that’s instantly accessible to designers anywhere to create and deliver new chip solutions faster than traditional approaches,” said Mohamed Kassem, co-founder and CTO at Efabless. “Through the CHIPS Alliance and other open source initiatives, we’re working to make it easier for design teams of all sizes to define, develop, collaborate and monetize their work.” 

At the CHIPS Alliance Workshop on Thursday, Sept. 17, Kassem and Andrew Kahng of OpenROAD and UCSD will be presenting the session “OpenROAD open RTL-to-GDS update.” The talk will discuss the OpenROAD autonomous and fully open flow for chip design.

“We’ve been impressed with Efabless’ strong commitment to accelerating open source chip innovation,” said Dr. Zvonimir Bandić, Chairman, CHIPS Alliance. “We look forward to working closely with Efabless and our other members to continue to lower the cost of developing IP and tools for hardware development.”

Efabless is collaborating with SkyWater Technology Foundry  and CHIPS Alliance members Google and Antmicro on an open source SkyWater PDK (Process Design Kit) for the 130 nm CMOS process technology. Efabless will make the design for this PDK simple and affordable by integrating resources on its cloud-based design platform including: an open source based end-to-end ASIC design flow – openLANE based on OpenROAD, Yosys and Magic; the open source striVe family of full ASIC reference designs; and a marketplace for monetizing chip and IP designs. This project will help lower the cost of entry for chip manufacturing, making chip design more accessible for everyone. 

Additionally, Efabless is managing the Open Source Shuttle Program sponsored by Google. This program will provide free of cost chip manufacturing runs for open source designs. The first run is scheduled for November 2020, and another will take place in early 2021.

To check out the schedule for the CHIPS Alliance Workshop and register for this free event, please visit: https://events.linuxfoundation.org/chips-alliance-workshop/program/schedule/.  

About the CHIPS Alliance

The CHIPS Alliance is an organization which develops and hosts high-quality, open source hardware code (IP cores), interconnect IP (physical and logical protocols), and open source software development tools for design, verification, and more. The main aim is to provide a barrier-free collaborative environment, to lower the cost of developing IP and tools for hardware development. The CHIPS Alliance is hosted by the Linux Foundation. For more information, visit chipsalliance.org.

About the Linux Foundation

The Linux Foundation was founded in 2000 and has since become the world’s leading home for collaboration on open source software, open standards, open data, and open hardware. Today, the Foundation is supported by more than 1,000 members and its projects are critical to the world’s infrastructure, including Linux, Kubernetes, Node.js and more. The Linux Foundation focuses on employing best practices and addressing the needs of contributors, users, and solution providers to create sustainable models for open collaboration. For more information, visit linuxfoundation.org.

 

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CHIPS Alliance Welcomes Mentor as its Newest Member

By Announcement

Mentor to present at the virtual CHIPS Alliance Workshop on Sept. 17 

SAN FRANCISCO, Aug. 18, 2020 – CHIPS Alliance, the leading consortium advancing common and open hardware for interfaces, processors and systems, today announced that Mentor, a Siemens business, has joined as its newest member. The CHIPS Alliance has a roster of more than 20 members collaborating to accelerate the creation and deployment of open system-on-chips (SoCs), peripherals and software tools for a wide range of applications.

“Mentor has a long history of supporting open standards to enable companies to design and verify their solutions,” said Badru Agarwala, general manager of Digital Design and Implementation Solutions at Mentor. “High level synthesis plays an important role in the design of accelerators, and in fostering an open and collaborative hardware development ecosystem. We look forward to contributing to the CHIPS Alliance’s efforts to reduce design barriers for the benefit of the entire silicon ecosystem.”

Mentor is a world leader in electronic hardware and software design solutions, providing products, consulting services and award-winning support for the world’s most successful electronic, semiconductor and systems companies. The company recently collaborated with another CHIPS Alliance member, Imperas Software, to extend the hardware design verification of RISC-V cores with industrial quality coverage methodologies. Mentor’s high level synthesis (HLS) tool, Catapult, enables hardware designers to use C++ or SystemC to describe functional intent and move up to a more productive abstraction level.

 “Over the past year we’ve focused on expanding our membership base and achieving new technical milestones as we work to make open source silicon a reality for mobile, computing, consumer electronics and Internet of Things applications,” said Dr. Zvonimir Bandić, Chairman, CHIPS Alliance. “We’re pleased to welcome Mentor to this dynamic, collaborative community driving the new era of hardware innovation.” 

Mentor will be presenting at the CHIPS Alliance Workshop, being held virtually on Thursday, Sept. 17. Mentor’s Anoop Saha will be presenting the session “Open ML Accelerator.” 

To see the full CHIPS Alliance Workshop schedule and register for the event, please visit: https://events.linuxfoundation.org/chips-alliance-workshop/program/schedule/.

To learn more about CHIPS Alliance’s work, please check out the 2020 Annual Report: https://chipsalliance.org/chips-alliance-2020-annual-report/

About the CHIPS Alliance

The CHIPS Alliance is an organization which develops and hosts high-quality, open source hardware code (IP cores), interconnect IP (physical and logical protocols), and open source software development tools for design, verification, and more. The main aim is to provide a barrier-free collaborative environment, to lower the cost of developing IP and tools for hardware development. The CHIPS Alliance is hosted by the Linux Foundation. For more information, visit chipsalliance.org.

About the Linux Foundation

The Linux Foundation was founded in 2000 and has since become the world’s leading home for collaboration on open source software, open standards, open data, and open hardware. Today, the Foundation is supported by more than 1,000 members and its projects are critical to the world’s infrastructure, including Linux, Kubernetes, Node.js and more. The Linux Foundation focuses on employing best practices and addressing the needs of contributors, users, and solution providers to create sustainable models for open collaboration. For more information, visit linuxfoundation.org.

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Note: A list of relevant Siemens trademarks can be found here.

 

QuickLogic Joins CHIPS Alliance to Expand Open Source FPGA Efforts

By Announcement

QuickLogic to present at the virtual CHIPS Alliance Workshop on Sept. 17 

SAN FRANCISCO, Aug. 11, 2020 – CHIPS Alliance, the leading consortium advancing common and open hardware for interfaces, processors and systems, today announced that QuickLogic Corporation (NASDAQ: QUIK), a developer of ultra-low power multi-core voice-enabled SoCs, embedded FPGA IP, and Endpoint AI solutions, has joined as its newest member.

“Over the past few years the electronics industry has seen a big shift towards open source hardware and software, and we’re proud to be one of the companies at the forefront of that movement,” said Brian Faith, president and CEO at QuickLogic. “We have already been working closely with several CHIPS Alliance members to make FPGA tools and devices more accessible, and we look forward to continuing these efforts as an official member of the organization.”

QuickLogic recently announced the QuickLogic Open Reconfigurable Computing (QORC) initiative to broaden access to open FPGA technology for embedded systems developers. QuickLogic’s initial open source development tools, developed in collaboration with CHIPS Alliance members Antmicro and Google, include complete support for QuickLogic’s EOS S3 low power voice and sensor processing MCU with an integrated embedded FPGA (eFPGA), and its PolarPro 3E discrete FPGA family. 

Additionally, QuickLogic and Antmicro launched the first fully open source Arm Cortex M4 MCU + eFPGA SoC dev kit, QuickFeather™. Antmicro added support for the QuickFeather dev kit into the Zephyr Real Time Operating System (RTOS), as well as in its open source Renode simulation framework. This small form factor development board is ideal for low-power machine learning (ML) capable IoT devices.

Said Dr. Zvonimir Bandić, Chairman, CHIPS Alliance: “The CHIPS Alliance is continuing to focus on expanding its member base with organizations from a diverse set of industries. QuickLogic, a leader in open source eFPGA IP and FPGA tooling, will help us drive innovation in the FPGA sector and further our mission to remove barriers for open hardware design.”

QuickLogic’s Brian Faith will present “Open Source FPGA Tooling, Our Journey from Resistance to Adoption” at the CHIPS Alliance Workshop, being held virtually on Thursday, September 17.

To see the full CHIPS Alliance Workshop schedule and register for the event, please visit: https://events.linuxfoundation.org/chips-alliance-workshop/program/schedule/.

About the CHIPS Alliance

The CHIPS Alliance is an organization which develops and hosts high-quality, open source hardware code (IP cores), interconnect IP (physical and logical protocols), and open source software development tools for design, verification, and more. The main aim is to provide a barrier-free collaborative environment, to lower the cost of developing IP and tools for hardware development. The CHIPS Alliance is hosted by the Linux Foundation. For more information, visit chipsalliance.org.

About the Linux Foundation

The Linux Foundation was founded in 2000 and has since become the world’s leading home for collaboration on open source software, open standards, open data, and open hardware. Today, the Foundation is supported by more than 1,000 members and its projects are critical to the world’s infrastructure, including Linux, Kubernetes, Node.js and more. The Linux Foundation focuses on employing best practices and addressing the needs of contributors, users, and solution providers to create sustainable models for open collaboration. For more information, visit linuxfoundation.org.

 

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CHIPS Alliance Announces AIB 2.0 Draft Specification to Accelerate Design of Open Source Chiplets

By Announcement

AIB reduces design barriers, costs, and leverages generators to ease development of  chiplet-based designs

SAN FRANCISCO, July 16, 2020 – CHIPS Alliance, the leading consortium advancing common and open hardware for interfaces, processors and systems, today announced that it has released the Advanced Interface Bus (AIB) version 2.0 draft specification on GitHub. The AIB standard is an open-source, royalty-free PHY-level standard for connecting multiple semiconductor die within the same package. AIB is ideal for designing SoCs, FPGAs, SerDes chiplets, high-performance ADC/DAC chiplets, optical networking chiplets and more. 

AIB 2.0 has more than six times the edge bandwidth density of AIB 1.0 through increases in the per-wire line rate and the number of IOs per channel. Additionally, with smaller microbumps AIB 2.0 can use as little as half of the current microbump array area. AIB makes it easier for designers to connect chiplets so companies can mix foundries, process nodes, IP sources, etc. for more flexibility in designing highly-integrated semiconductor devices. 

“The AIB 2.0 draft standard continues the CHIPS Alliance’s efforts to provide comprehensive design resources to simplify hardware design and reduce development costs,” said Dr. Zvonimir Bandić, Chairman, CHIPS Alliance. “As companies increasingly rely on chiplets to keep up with the latest computing requirements and workloads for different applications, AIB will make it easier to integrate silicon IP with other chiplets into a single device to deliver new levels of functionality and optimization.”

The CHIPS Alliance and its members are working together to help foster the growth of an industry ecosystem which engenders more device innovation via heterogeneous integration. With broader adoption and support for AIB-enabled chiplets, developers can go beyond the limits of traditional monolithic semiconductor manufacturing to leverage the ideal process node for each function in their design while lowering development costs. The AIB specification is already in use by leading semiconductor companies, and has also been adopted by DARPA’s Common Heterogeneous Integration and IP Reuse Strategies (CHIPS) program.

To further reduce the design effort of producing block variants and porting custom blocks to a new process, Blue Cheetah Analog Design, Inc. has developed agile, process portable, and parameterizable generators for the AIB die-to-die interface. Blue Cheetah’s AIB PHY Generator enables the rapid generation of sign-off ready AIB custom blocks (i.e. netlist, GDS, LEF, LIB, and behavioral models) across a multitude of process design kits (PDKs).

“Reducing barriers to entry in developing custom silicon will be critical for the growth, adoption, and success of the chiplet movement,” said Dr. Krishna Settaluri, CEO, Blue Cheetah Analog Design. “By producing custom blocks at push-button speed, Blue Cheetah’s generators drastically reduce time-to-market and engineering effort required to produce tape-out ready IP. We are excited to offer this capability and look forward to enabling companies to thrive in the chiplet ecosystem.”

Dr. Settaluri of Blue Cheetah and David Kehlet of Intel® Corporation will be discussing the AIB PHY generator and AIB 2.0 draft specification at DAC 2020, which is being held virtually this year. The session, called “Tutorial 10 Part 1: Chiplet Integration: Tools, Methodology, Requirement, Infrastructure,” will take place on Monday, July 20 at 1:30 p.m. PT. To learn more about the talk, please visit here

To read the AIB specification, please visit: https://github.com/chipsalliance/AIB-specification.

To check out the AIB PHY Generator, please visit: https://github.com/chipsalliance/aib-phy-generator

About the CHIPS Alliance

The CHIPS Alliance is an organization which develops and hosts high-quality, open source hardware code (IP cores), interconnect IP (physical and logical protocols), and open source software development tools for design, verification, and more. The main aim is to provide a barrier-free collaborative environment, to lower the cost of developing IP and tools for hardware development. The CHIPS Alliance is hosted by the Linux Foundation. For more information, visit chipsalliance.org.

About the Linux Foundation

The Linux Foundation was founded in 2000 and has since become the world’s leading home for collaboration on open source software, open standards, open data, and open hardware. Today, the Foundation is supported by more than 1,000 members and its projects are critical to the world’s infrastructure, including Linux, Kubernetes, Node.js and more. The Linux Foundation focuses on employing best practices and addressing the needs of contributors, users, and solution providers to create sustainable models for open collaboration. For more information, visit linuxfoundation.org.

 

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CHIPS SweRV Cores and the Open Tools Ecosystem

By Blog

This post was originally published at Antmicro.

Antmicro’s open source work spans all parts of the computing stack, from software and AI, to PCBs, FPGAs and, most recently, custom silicon. We connect those areas with an overarching vision of open source tooling and methodology, and a software-driven approach that allows us to move fast and build future-centric solutions. Our partners and customers, many of whom work with us also in the context of organizations such as CHIPS Alliance and RISC-V, share our approach to developing open systems. We were recently very happy to be invited to give a talk at the “Production grade, open RISC-V SweRV Core Solutions in CHIPS Alliance” meetup organized by Western Digital where we presented our systems approach on the example of the open source tools ecosystem that targets their SweRV cores and which we are helping to develop.

What is SweRV?

SweRV is a family of production-grade RISC-V implementations originally developed by Western Digital, who have announced they are going to transition 2 billion cores in their products to RISC-V, showing they are fully committed to this open processor architecture. SweRV comes in three variants: the original EH1 and the recently released EH2 and EL2.

EH2 is the world’s first dual-threaded commercial, embedded RISC-V core designed for IoT and AI systems, boasting as much as 6.3 CoreMark/MHz in dual-threaded mode, at 1.2 GHz in 16nm. EL2, on the other hand, is a tiny, low-power but high-performance RISC-V core (with just 0.023 mm2 in 16nm, it runs at up to 600 MHz and 3.6 CoreMark/MHz) targeting applications such as state-machine sequencers and waveform generators. The best thing about them is that anybody can use and extend them for free, with more high performance cores being planned in the future.

But a CPU is as good as the tooling around it and Western Digital knows it. That is why the entire SweRV family was handed over to CHIPS Alliance, which now aims to facilitate using the cores in practical scenarios by maintaining the dynamic ecosystem of relevant tools. Many of the necessary building blocks are already in place, while others are still being developed with active participation of Antmicro, the FOSSi community and others. In this article you will see examples of how you can work with SweRV in simulation, on an FPGA and in an ASIC context.

Getting started

To get started very quickly with no hardware whatsoever, you can simulate any of the SweRV cores in Verilator – one of the most successful and widely used open source projects in the EDA space, which we use extensively. Simply, go to the relevant core’s GitHub space in the CHIPS Alliance organization (e.g. https://github.com/chipsalliance/Cores-SweRV for EH1) and simulate the RTL (which is written in SystemVerilog).

Verilator simulates the RTL with high performance by compiling to an optimized model and running it, outperforming many proprietary alternatives. What is more, it is developing very fast thanks to the work of its maintainer – Wilson Snyder, the FOSSI community and CHIPS Alliance. Antmicro specifically has been working together with Western Digital and Google on adding support for SystemVerilog / Universal Verification Methodology to enable Verilator’s design verification for real-world use cases (see Looking into the future below).

Putting SweRV into an FPGA

If you want to get working on something more tangible, you might want to run SweRV on an FPGA – in a portable, vendor-neutral manner, of course.

To simplify interfacing with various toolchains, simulators and other tools you might need depending on the platform you want to target, you can use Edalize – a Python utility that allows you to seamlessly work with different kinds of EDA tools, both for FPGA and ASIC design. It helps you to maintain consistent workflows and pinpoint whether a specific bug is tool-related or pertains to your code. We’ve been adding quite a lot of new functionalities into Edalize recently, while using it heavily as a default way to interface with various tools out there in our work e.g. sv-tests (again, see Looking into the future for more on that topic).

Edalize will help you use your SweRV-based design on the FPGA/board of your choice without having to care about remembering and maintaining specific configurations and runtime flags.

Another great tool from the same author is FuseSoC, a Python-based package manager and a set of build tools for HDL code. It enables you to reuse your FPGA IP across many designs and, of course, it supports SweRV cores well. Apart from making it simple to reuse existing cores, it allows you to easily create compile-time or run-time configurations, port designs to new targets, set up configurable Continuous Integration as well as let other projects use your code. FuseSoC is also used by the SweRVolf SoC.

Thanks to integrations with other open source tools like Google’s Verible linter/formatter, that we’re also helping to develop, FuseSoC can be used to lint and format System Verilog – we have recently written an article about this.

Incorporating SweRV into an SoC

A core alone, however, is not enough to get any practical work done. If you want to build a System-on-Chip, you should definitely look at LiteX – a SoC generator that allows you to put SweRV in an actual use case. LiteX is an IP library and a SoC builder that is portable between various FPGAs and can turn SweRV into a full blown system. It has a number of IPs and other building blocks such as Ethernet, RAM, UART, SATA, etc. which you can configure to work with different kinds of CPUs. It has initial SweRV support which enables the user to quickly build plug & play SoC systems with SweRV. Antmicro is heavily involved in work to build a robust ecosystem around it. LiteX can run the Zephyr RTOS – which is also supported on SweRV – and, with a suitable CPU, it can run Linux as well. The LiteX SoC ecosystem can also be used together with another tooling project we heavily contribute to, SymbiFlow – the open source FPGA flow.

Simulating, experimenting, testing

If you want to use SweRV to build a full production system and leverage the flexibility to customize that comes with the RISC-V and open tooling, you will most likely need to experiment with the architecture and co-develop hardware and software. This is where Renode can be of immense use thanks to its architectural exploration, simulation, testing and debug capabilities for complex systems: entire SoCs, boards and systems of boards. All you need to do is download Renode and put together a few configuration files – it even comes with many demos and pre-compiled examples for various platforms. Renode provides initial support for SweRV EH1 (with more to come) as well as extensive support of LiteX, which will let you quickly build and simulate entire open source SoCs. On top of that, Renode enables hardware/software co-simulation with Verilator for building your custom IP and testing its HDL as-is, while keeping the rest of the system simulated in Renode to save development time.

Building and verifying a production-grade ASIC

Assuming SweRV fits your use case, you may eventually want to build and verify a production-grade ASIC which includes one of those CPUs. As part of the CHIPS working groups focused on cores and tools, the developers of SweRV in collaboration with Google, Antmicro and others are building an entirely open source design verification ecosystem around the cores family, including projects such as riscv-dv and Whisper ISS. The former is an entire SV/UVM flow based on an instruction generator for RISC-V processor verification, which allows you to perform various tests on SweRV-based designs. It features a number of test suites dedicated to different functionalities. It runs ISS and RTL simulators in tandem and compares the results. Whisper ISS is a tool used for verification of SweRV implementations, which can be run in an interactive mode, allowing the user to single step RISC-V code and inspect/modify the RISC-V registers or system memory, or it can be run in lock-step, e.g. with Verilator.

Looking into the future

There is ongoing work from CHIPS Alliance and the broader open source community to rapidly transform the ASIC-development workflows to fully embrace open source. One such effort is sv-tests, a System Verilog test suite designed to stress-test different kinds of designs in SystemVerilog against various open source tools, showing a results table indicating detailed coverage. SweRV, being written in SystemVerilog, is of course one of the suite’s test targets.

The SV test suite informs some of our ongoing open source work for ASIC tooling, one of the goals of which is to enable open source development and verification of System Verilog designs. An interesting tool to look at in this space is Surelog – a full-blown SystemVerilog parser developed in collaboration between Google and Antmicro oriented at simulation and UVM. We are working to plug it as the System Verilog front-end into various open source tools using a framework called UHDM (Universal Hardware Data Model), which will enable code reuse between various tools with similar needs.

With the recent release of the world’s first open PDK, that we are proud to have been participating in, and the progress being made in the OpenROAD project, which aims at a fully open flow for chip design and other areas, it looks like the future in which a SweRV based SoC can be designed, verified and manufactured using open tools is not that far off.

Summary

Apart from being an expanding, production-grade family of cores, SweRV taps into a very good and dynamic ecosystem of tools that we are helping to build. CHIPS Alliance is aiming to revolutionize the way developers work with ASICs and FPGAs by enabling a software-driven approach to silicon, which perfectly aligns with Antmicro’s strategy and long-term objectives. With extensive experience in RISC-V-powered open source work, we offer high-quality services that our customers can use to build on top of SweRV using these new collaborative methodologies and tools. Reach out to Antmicro at contact@antmicro.com to find out how the company can assist you with your next RISC-V-centered project.

Open Source Process Design Kit from Google, SkyWater Technologies and Partners Released

By Blog

This post was originally published at Antmicro.

The ASIC design and manufacturing flow has for a long time been dominated by proprietary tools and processes. The growing complexity of chip-building has been reinforcing the claim that “hardware is too hard to be open source”, as the cost and time needed to build an ASIC have kept small, more agile, software-oriented teams and individuals away from the hardware domain. Thus, ASICs have not been able to benefit from the enthusiasm and collaboration which have been fuelling software development for decades now. Thanks to the continued effort of many entities which Antmicro is very proud to be among, this is now changing quickly.

RISC-V: Openness-driven innovation

The first shift in the walled garden, proprietary chips design landscape came with the creation of the RISC-V Foundation in 2015 centered around the open source RISC-V ISA. Antmicro has been on board as a Platinum Founding Member of the Foundation (now, several hundred members strong, transitioning into a Swiss-based entity called RISC-V International) since the very beginning, as it reflected our belief that an open source approach can – and is bound to, eventually – revolutionize all areas of computing, even the less obvious ones.

RISC-V proved ASIC design can be a collaborative process, with players big and small working together to compliment each other’s strengths not only in developing the ISA but also many of the tools needed to make it practically useful. For example, Microsemi worked with SiFive to provide the SoC complex at the heart of their new and exciting PolarFire FPGA SoC, and then turned to Antmicro to provide a simulation environment – using our open source Renode Framework – to make development possible before the SoC hits the market later this year. The OpenTitan project, driven by key RISC-V adopters Google and Western Digital together with the UK not-for-profit lowRISC, strives to build a more transparent, trustworthy, high-quality reference design and integration guidelines for silicon Root of Trust chips. Such examples abound in the RISC-V world, but the un-core, design tools, verification and other parts of the ecosystem have mostly remained closed.

Enter CHIPS

Established in 2019, CHIPS Alliance takes the open, collaborative aspect of RISC-V even further. CHIPS wants to generate and integrate fully open source, high quality IP and tooling for ASIC design; the organization extends beyond cores and specifications, and acknowledges the importance not only of the result but the process itself; thus, the aim is to make both ASICs and the ASIC design processes open source all the way. Why? Again, a lesson learned from software: if you open up to collaboration, adaptation and change on all levels, the long-term results will be surprisingly good.

CHIPS has been home to such important projects as the Chisel HDL, the Rocket core generator and related tools, the SweRV cores or AIB interconnect. There is work under way to enable fully open source SystemVerilog/UVM support in tools like Verilator and Yosys (with some milestones like fully open source linting, formatting or synthesis of SystemVerilog code already accomplished), opening the door to more open source collaboration around design verification which constitutes the highest cost in modern chip design.

Also in the tools area, the very ambitious OpenROAD project, also a CHIPS member, is a DARPA-backed activity aiming to create a fully open source, quick, automated digital design flow. If you want to see how open source, automated chip design might look like in the future, see OpenROAD’s excellent ChipKit tutorial from ISCA 2020.

Aggregating those activities a vastly different landscape begins to emerge, one where chip design can be innovated upon on various levels, and teams can go back and forth between hardware and software optimizations for new use cases such as machine learning without NDAs and costly licences. But – until now – there was one element notably missing.

First ever open source PDK

We are excited to announce Antmicro’s participation in yet another historic first in the area of semiconductor process technology. In a project led by Google and SkyWater Technology, and in collaboration with partners including Antmicro, Blue Cheetah, efabless and numerous Universities, an open source SkyWater PDK (Process Design Kit) for the 130 nm MOSFET fabrication process, along with related sources, is being made available. This development greatly lowers the cost of entry into chip manufacturing and paves the way for even more exciting collaborations to happen in the open source silicon domain.

For some background, a PDK is a set of data files and tools used to model a specific process in a given foundry used with EDA (Electronic Design Automation) tools in the chip design flow. PDKs traditionally have been closed – to the point where some would say it’s impossible to make them open! This collaboration, where Antmicro worked together with Google and efabless to convert the PDK data for the public release, is an important step towards truly open source chips. The 130nm PDK process is a mature technology that is useful for a range of applications, especially in the area of microcontroller development and research as well as mixed signal embedded designs and other use cases which combine digital and analog circuits. The SKY130 technology stack consists of:

  • 1 level of local interconnect
  • 5 levels of metal
  • Inductor-capable
  • High sheet rho poly resistor
  • Optional MiM capacitors
  • Includes SONOS shrunken cell
  • Supports 10V regulated supply
  • HV extended-drain NMOS and PMOS

SkyWater is an American technology foundry accredited by the US Department of Defense, which offers custom integrated circuit design and manufacturing services. It is predicted that the launch of the open source SKY130 process node will be followed by other, more advanced nodes, ultimately enabling more advanced processor applications, including ones that are Linux-capable.

The inaugural talk by Tim Ansell

On Tuesday, June 30 at 16:00 GMT, Google’s Tim Ansell will give a talk at the FOSSi Dial-up meeting, presenting a thorough overview of the technical details of the PDK, as well as outlining the project’s goals and its roadmap. The event will be livestreamed on YouTube and will be followed by a Q&A session, so tune in to find out more about this historic step towards an open, accessible and collaborative chip-making process.

Semiconductor Engineering: About The SweRV Core EH2

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In mid-May, CHIPS Alliance announced the open sourcing of the SweRV Core EH2 and SweRV Core EL2 designed by Western Digital. These cores, as well as the earlier EH1, are now supported by Codasip’s SweRV Core Support Package which provides all of the components necessary to design, implement, test, and write software for a SweRV Core-based system-on-chip. But what is SweRV Core EH2?

The SweRV Core EH1 was the first to be released through CHIPS Alliance and was a core aimed at high-end embedded applications including Western Digital’s flash controllers and SSDs. The core is a dual issue, superscalar, high-performance core with 9 pipeline stages. The EH2 is an exciting further development aimed at delivering even more performance for IoT, artificial intelligence and data-intensive embedded applications.

To read more, please check out the article at Semiconductor Engineering written by Roddy Urquhart at Codasip: https://semiengineering.com/about-the-swerv-core-eh2/.

QuickLogic Announces Open Reconfigurable Computing Initiative

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Originally issued by QuickLogic, the following press release announces the QORC initiative including the world’s first vendor-supported open FPGA toolchain using SymbiFlow, and describes the contribution of CHIPS Alliance members Antmicro and Google.


  • QuickLogic Open Reconfigurable Computing (QORC) initiative, developed by Antmicro in collaboration with QuickLogic and Google, broadens access to company’s FPGA technology and eFPGA IP for all embedded systems developers
  • First Programmable Logic Company to Embrace Open Source FPGA Development Tools

San Jose, CA – June 16, 2020 – QuickLogic Corporation (NASDAQ: QUIK), a developer of ultra-low power multi-core voice-enabled SoCs, embedded FPGA IP, and Endpoint AI solutions, today announced its ground breaking QORC (QuickLogic Open Reconfigurable Computing) initiative, making it the first programmable logic vendor to actively embrace a fully open source suite of development tools for its FPGA devices and eFPGA technology. This initiative engenders the emerging trend toward open source tooling, significantly broadens access to the company’s products, and enables both hardware and software developers with tools supported by both the user community and QuickLogic.The company’s initial open source development tools, developed by Antmicro in collaboration with QuickLogic and Google, include complete support for its EOS S3 low power voice and sensor processing MCU with embedded FPGA, and its PolarPro 3E discrete FPGA family. Support for additional QuickLogic products, including QuickAI and support for its eFPGA IP offering will be added over the next few months.

EOS S3 Open Source Development Tools:

  • FPGA Development Flow: SymbiFlow – Open source tools for the optimization and automation of the FPGA design flow, from Verilog to bitstream generation. These tools enable innovation by making FPGAs more accessible to a broader community.
  • SoC Emulation: Renode – Antmicro’s Renode is an open source simulation framework for rapid prototyping, development and testing of multi-node systems. Utilizing Renode gives developers the flexibility to fully evaluate multiple development board applications.
  • Zephyr Real Time Operating System (RTOS) – The Zephyr RTOS is an open source, vendor-neutral, compact, real-time operating system running on the Arm Cortex® M4F for connected, resource-constrained and embedded devices in applications that require security and safety.
  • QuickFeather Development Kit – A small form factor, 100% open source hardware development kit ideal for the next generation of low-power Machine Learning (ML) capable IoT devices.

Traditionally, programmable logic vendors offered and supported only proprietary synthesis, place and route tools. Open source tools were relegated to hobbyists, academics, and independent consultants. However, the electronics industry is starting to see a shift toward open sourced hardware and software as it provides flexibility, vendor and community support, longevity, and adaptability to each engineer’s design flow. Google and Antmicro have been noteworthy influencers in this market, increasing the breadth of supported architectures and quality of results for the open source tools. They are now not only viable but desirable for the majority of the development community, including design teams at many of the industry’s largest companies.

“QORC is QuickLogic’s initiative to embrace the rapidly growing open source FPGA tooling ecosystem, inspiring engineers to collaborate on the creation of exciting and innovative products,” said Brian Faith, QuickLogic’s president and CEO. “We believe that the wide adoption of open source tools represents a paradigm shift for the industry, and we’re proud to be at the leading edge.”

“With its open source-centered approach, Antmicro has been moving the technological frontier, building whole ecosystems of non-proprietary solutions and overcoming the limitations inherent in closed technologies,” said Michael Gielda, Antmicro’s VP of Business Development. “We’ve been excited to participate in this historical first from QuickLogic, by contributing our expertise in software, hardware and tools to implement the necessary SymbiFlow, Renode and Zephyr support for their hardware platform – broadening their reach within the developer community.”

Availability

SymbiFlow FPGA, Renode SoC Emulation, and Zephyr RTOS support are available now for QuickLogic’s EOS S3 voice and sensor processing platform and PolarPro 3E FPGA products, as well as the new QuickFeather Development Kit. Support for QuickLogic’s embedded FPGA technology will be added later this year. To learn more, please visit www.quicklogic.com/QORC.

About QuickLogic

QuickLogic Corporation (NASDAQ: QUIK) is a fabless semiconductor company that develops low power, multi-core semiconductor platforms and Intellectual Property (IP) for Artificial Intelligence (AI), voice and sensor processing. The solutions include embedded FPGA IP (eFPGA) for hardware acceleration and pre-processing, and heterogeneous multi-core SoCs that integrate eFPGA with other processors and peripherals. The Analytics Toolkit from our recently acquired wholly-owned subsidiary, SensiML Corporation, completes the end-to-end solution with accurate sensor algorithms using AI technology. The full range of platforms, software tools and eFPGA IP enables the practical and efficient adoption of AI, voice, and sensor processing across mobile, wearable, hearable, consumer, industrial, edge and endpoint IoT. For more information, visit www.quicklogic.com and https://www.quicklogic.com/blog/.

QuickLogic and logo are registered trademarks and EOS and SensiML are trademarks of QuickLogic. All other trademarks are the property of their respective holders and should be treated as such.

Press Contact:

Andrea Vedanayagam
Veda Communications
408.656.4494
pr@quicklogic.com

A Look Back at the CHIPS Alliance’s Incredible Growth

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It’s been just over a year since the CHIPS Alliance was founded with the mission of making open source hardware development more accessible to companies, universities and individuals. We’re working to bring the dynamics of the hugely successful open source software development model into ASIC design, building on the groundwork set by the RISC-V community. Progress over the past year is detailed in our Annual Report

 CHIPS Alliance is focused on expanding on this open hardware vision by:

  • Targeting other parts of ASICs beyond the CPU core, gradually open sourcing all IPs that go into a SoC, both analog and digital.
  • Open sourcing the tools needed to work with ASICs, making it possible to design innovative solutions without a massive upfront investment.
  • Providing real, battle-proven reference implementations and project infrastructure to ensure the continued success of the projects we govern and support.

 With these three pillars guiding our efforts, we believe that the CHIPS Alliance will enable truly open hardware to flourish for the first time. The CHIPS Alliance has already made incredible progress so far. We have achieved a number of important technical milestones, including announcing newly enhanced SweRV Cores – EH2 and EL2 – and releasing the Advanced Interface Bus (AIB) specification and reference implementations by one of the CHIPS Alliance’s newest members, Intel. These technical accomplishments are making it easier for engineers to design innovative embedded applications for the latest computing requirements.

We’re also excited by the significant community interest in the work we’re doing. Hundreds of people from around the world have attended CHIPS Alliance events over the past year, both in-person and online, and our working groups are running full steam ahead. Check out our Annual Report to learn more about the CHIPS Alliance’s news and activities, and stay up to date by following us on Twitter and LinkedIn.