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CHIPS Alliance to Reveal Project Details, Strategy and Roadmap at Inaugural Workshop Hosted at Google

By Announcement

SAN FRANCISCO –  May 7, 2019 – CHIPS Alliance, the leading consortium advancing common, open hardware for interfaces, processors and systems, today announced it is holding its inaugural workshop on June 19, 2019 at Google at 111 W. Java Drive, Sunnyvale, Calif.

Project details, strategy and roadmaps will be presented by member companies, and attendees will have an opportunity to propose Register Transfer Level (RTL) projects and development flow ideas. The workshop will focus on open source hardware, software tools, RTL development, design verification tools and related topics. The agenda and registration details are available at

“This workshop at Google will kick off CHIPS Alliance hardware RTL development. The organization will discuss the planned projects, what is needed for accelerated open source hardware and key software tools. Attendees will see the potential of CHIPS Alliance and the vision for what we will deliver,” said Dr. Zvonimir Bandic, Western Digital and Chairman of the CHIPS Alliance Foundation.

“Workshop attendees will learn more about our organization and the open source hardware, verification flows/tools and software we will be developing. Attendees will also have an opportunity to suggest projects and meet with CHIPS Alliance members and the Board of Directors. We look forward to answering questions, discussing ideas and sharing the aspirations of the group,” said Dr. Richard Ho, Google and Board member of the CHIPS Alliance Foundation.

CHIPS Alliance members include Antmicro, Esperanto Technologies, Google, SiFive and Western Digital. The Alliance is a collaborative forum designed to accelerate the creation and deployment of more efficient and flexible CPUs, SoCs and complex peripherals for FPGAs and custom silicon. It is supported by a Board of Directors and a Technical Steering Committee.

CHIPS Alliance Inaugural Workshop Agenda

  • 9:00   Introduction to CHIPS Alliance (Zvonimir Bandic)
  • 9:15   Why open source hardware unlocks innovation (Martin Fink)
  • 9:40      Federation: An Open-Source Chip Design Workflow  (Yunsup Lee)
  • 10:05    Collaborative end to end Design Verification Flow  (Richard Ho)
  • 10:30  Break
  • 11:00  RISC-V SweRV Core contribution (Zvonimir Bandic)
  • 11:20  Open Source Tools: cocotb and Verilator support  (Michael Gielda)
  • 11:40  Verilator and Test Bench Environment roadmap (Wilson Snyder)
  • 12:00  Lunch
  • 1:00    A natural fit, RISC-V with CHIPS Alliance (Naveed Sherwani)
  • 1:25    BooM v2 coordination with UC Berkeley (Dave Ditzel)
  • 1:50    Audience Participation – What RTL IP do you want to be designed?
  • 2:30   Break
  • 3:00   Blue Cheetah Framework for Rapid IP Design (Krishna Settaluri)
  • 3:25   FuseSoC support for SweRV (Olof Kindgren)
  • 3:40   Chisel and FIRRTL  (Yunsup Lee)
  • 4:00   Why join CHIPS Alliance? (Ted Marena)


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