CHIPS Alliance 2021 Annual Report

CHIPS Alliance was founded in March 2019 to design high-quality, open source hardware register transfer level (RTL) and develop open source hardware and software design tools. By creating an open and collaborative environment, companies and organizations can develop innovative, cost effective hardware designs optimized for the requirements of today’s silicon devices and FPGAs.

CHIPS Alliance was incorporated by four organizations which wanted to make open source silicon a reality. Esperanto, Google, SiFive and Western Digital were the founding members. Now almost two years later, it is fitting to look back at our progress. We are pleased to present this annual report detailing the many things we have accomplished collectively in this fast growing organization.

Comments and feedback are welcome at info@chipsalliance.org.

CHIPS Alliance is a barrier free, open organization focused on developing open source hardware RTL and open source hardware and software development tools. The organization desires to lower the cost of chip development through collaboration, leveraging the diverse expertise and broad experience of its members. CHIPS Alliance encourages contributions and shared investments by providing vendor-neutral promotional events, documentation, tools and support for a variety of projects in our workgroups.

Rob Mains serves as General Manager of the CHIPS Alliance. Rob joined the organization in January 2021, bringing more than 38 years of industry experience to the role. To learn more about Rob, please visit here. 

The following workgroups are part of CHIPS Alliance:

• Interconnect (currently OmniXtend, the AIB chiplet interface and TileLink)
• Cores (including the SWeRV core family)
• Tools (grouping efforts around extending Verilator to allow UVM-based DV, SystemVerilog support in open source, the RISC-V DV framework as well as tools like Cocotb and FuseSoC)
• Chisel (concerning the development of the Chisel HDL, FIRRTL intermediate representation and related tools)
• Rocket SoC (encompassing the Rocket core generator ecosystem)

The organization is also working on setting up an Open Source Analog Design/Generators Working Group.

In March 2019, CHIPS Alliance was formed as a project under the Linux Foundation. The four founding members – Esperanto, Google, SiFive and Western Digital – set the aspirations for the group. CHIPS Alliance can be viewed as an extension of the mission started by organizations such as RISC-V International. RISC-V defines an open instruction set architecture (ISA) specification which paved the way for a plethora of open cores and CPU implementations, but does not instruct how to make the physical hardware and other building blocks needed to create practical open silicon. This is where CHIPS Alliance begins. Using open standards such as RISC-V, CHIPS Alliance is working to collaboratively build robust and industry-proven cores, peripherals and SoCs. 

Early on it became clear that lowering the barriers and cost of development would require collaboration among many parties to develop relevant open source design tools. CHIPS Alliance stepped up to the task. Today the organization focuses on both open source hardware RTL designs and open source software and hardware design tool development. CHIPS Alliance is a barrier free, open organization promoting open silicon.

CHIPS Alliance has grown to more than 25 members over the past year. The organization now boasts some of the world’s leading semiconductor manufacturers including Intel, Samsung, Futurewei and Alibaba. Software tools, IP and services companies in the organization include Antmicro, Codasip, Imperas, Qamcom and Verisilicon. Several notable universities and open source projects are also part of CHIPS Alliance such as UC Berkeley, IIT Madras, Yale University, OpenRoad, Munich University of Applied Sciences and UC San Diego. The complete membership list can be found at https://chipsalliance.org/about/members/

To aid new members and those who are interested in knowing more about CHIPS Alliance, we have created a Getting Started Guide. We encourage everyone to join our main mailing list, follow us on social media channels Twitter and LinkedIn, and engage in our technical community, which is not limited to members. If you see a particular workgroup you want to get involved in, you can join that specific mailing list and attend their meetings.

CHIPS Alliance hosted a number of events over the past year, pivoting to virtual workshops and Meetups due to the pandemic. Below please find more information about the events CHIPS Alliance and its members participated in:

• In January 2020, CHIPS Alliance hosted a Chisel Community Conference at Western Digital’s Milpitas office. The two day event featured talks from industry leaders and academia, as well as in-depth training on Chisel, FIRRTL and the associated software ecosystem.
• In April 2020, CHIPS Alliance held an online meetup on Cache Coherent Memory Fabric with TileLink and OmniXtend. There were over 250 attendees who learned about developments from SiFive, Western Digital and Intel.
• In May 2020, the CHIPS Alliance participated in a Meetup hosted by the  Bay Area RISC-V Group, providing attendees with an overview of the organization and the SweRV family of cores. 
• In September 2020, the CHIPS Alliance Workshop featured 10 talks about open source milestones, progress, updates and more. 
• In November, CHIPS Alliance chair of Outreach Committee Michael Gielda gave a talk at RISC-V Days Tokyo, discussing the ongoing activities towards enabling fully open source and CI-driven ASIC and FPGA development flows.
• In December 2020, at the RISC-V Summit, CHIPS Alliance Chairman Dr. Zvonimir Bandić gave a talk about OmniXtend, and Antmicro gave a talk describing its efforts towards enabling SystemVerilog support in open source tools.

• CHIPS Alliance announced a collaboration with RISC-V International to standardize an open unified memory coherency bus leveraging OmniXtend to foster innovation for data-centric applications.
• CHIPS Alliance released the Advanced Interface Bus (AIB) version 2.0 draft specification on GitHub. The AIB standard is an open-source, royalty-free PHY-level standard for connecting multiple semiconductor die within the same package.
• Antmicro and Western Digital have been making significant progress in enabling dynamic scheduling in Verilator, which paves the way for open source UVM verification.
• The CHIPS Alliance announced the enhanced updates of the SweRV Core EH2 and EL2 solutions which were initially developed by Western Digital. The SweRV Core family also includes the EH1. Learn more at GitHub.
• Antmicro, Google and the CHIPS Alliance have been working together with the lowRISC project to develop Verible linting and formatting support (including FuseSoC integration) for some SystemVerilog features required for working with practical use cases, such as lowRISC’s ibex. Ibex can also now be synthesized and simulated in a completely open source flow using Surelog, Yosys and Verilator.
• Google, SkyWater, eFabless, Antmicro, the OpenROAD project and other partners collaborated to release the first ever open source process design kit, SkyWater’s PDK for the 130 nm MOSFET fabrication process, along with related sources. This development lowers the cost of entry into chip manufacturing and paves the way for even more exciting collaborations to happen in the open source silicon domain.
• Antmicro and Google have been further developing the open source SystemVerilog test suite. It is available on GitHub. The suite runs a number of open source EDA tools against a series of SystemVerilog compliance tests and presents the results online.
• The SweRV Support Package (SSP), developed by Codasip in cooperation with Western Digital, provides a comprehensive set of tools and components for designing, implementing, testing and writing software for a SweRV Core-based SoC. The basic version of the SSP is available free of charge at GitHub.
• The SweRV Instruction Set Simulator (ISS), initially developed by Western Digital, offers full test bench support for the design of SweRV Cores.
• The Chisel workgroup has also achieved a significant number of technical milestones, as presented on the 2020 Chisel Community Conference

The members of CHIPS Alliance join for a variety of reasons. Some organizations join to grow their business. Companies that fall into this group normally offer an open source solution, along with selling support and additional services to interested companies. As an example, Codasip has an open SweRV package that anyone can access, a Pro version with commercial EDA tools, and customization and verification services available upon request.

Many organizations join CHIPS Alliance to accelerate development of a RTL IP/SoC or software tool. For example, the software tool Verilator and the hardware compiler framework Chisel have benefited from their organizations joining. See slide 4 of the Verilator, Accelerated presentation to see how CHIPS Alliance has benefited the Verilator ecosystem.

Another reason companies join CHIPS Alliance is to accelerate adoption of IP or software. One such IP is AIB which was brought into CHIPS Alliance by Intel. AIB is a chiplet interconnect and is being adopted by a number of companies. DARPA presented on the benefits of AIB and how chiplets can accelerate SoC development.

Don’t miss the CHIPS Alliance Spring Workshop on March 30! Learn more and register for free. Sign up for our announcements list to be kept up-to-date on our events. The CHIPS Alliance has seen additional interest from a number of companies, organizations and nonprofits in joining our ecosystem, so we will continue to focus on growing our membership. As development accelerates and more output is generated, we anticipate this will foster even more interest in CHIPS Alliance and its open source solutions.