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CHIPS (Common Hardware for Interfaces, Processors and Systems) Alliance harnesses the energy of open source collaboration to accelerate hardware development.
This organization develops high-quality, open source hardware designs relevant to silicon devices and FPGAs. By creating an open and collaborative environment, CHIPS Alliance shares resources to lower the cost of development. Companies and individuals can work together to develop open source CPUs, various peripherals, and complex IP blocks. CHIPS Alliance is open to all organizations who are interested in collaborating on open source hardware or software tools to accelerate the creation of more efficient and innovative chip designs.
Support For Chips Alliance
“Open collaboration has repeatedly proven to help industries accelerate time to market, achieve long-term maintainability, and create de facto standards. The same collaboration model applies to the hardware in a system, just as it does to software components. We are eager to host the CHIPS Alliance and invite more organizations to join the initiative to help propel collaborative innovation within the CPU and SoC markets.”Mike Dolanvice president of strategic programs, the Linux Foundation
“As new workloads surface every day, we need new silicon designs in order to optimize processing requirements. Today’s legacy general-purpose architectures are, in some cases, decades old. With the creation of the CHIPS Alliance, we are expecting to fast-track silicon innovation through the open source community.”Martin Finkinterim CEO of RISC-V Foundation and executive vice president and CTO of Western Digital
“We are entering a new golden age of computer architecture highlighted by accelerators, rapid hardware development and open source architecture and implementations. Google is committed to fostering an open community of collaboration and innovation in both hardware and software. The CHIPS Alliance will provide the support and framework needed to nurture a vibrant open source hardware ecosystem for high-quality, well-verified and documented components to accelerate and simplify chip design.”Dr. Amir Saleksenior director, Technical Infrastructure, Google Cloud
“Semiconductor design starts have evaporated due to the skyrocketing cost of building a custom SoC. A healthy, vibrant semiconductor industry needs a significant number of design starts, and the CHIPS Alliance will fill this need. SiFive is excited to continue to work on and contribute to the RocketChip SoC generator, TileLink, Chisel, and FIRRTL projects as we push the boundaries of open source innovation.”Dr. Yunsup Leeco-founder and CTO, SiFive
CHIPS Alliance will be adding projects over time as the community gets started. Two initial projects are highlighted below. These projects represent the beginning; CHIPS Alliance will eventually include additional projects from across the SOC and CPU ecosystem. We welcome code, engineer involvement, and partnership collaborations to further define and focus projects into relevant and strategically critical opportunities. Please reach out to CHIPS Alliance directly with questions or ideas.
We invite all developers who are interested in contributing to CHIPS Alliance to sign up to stay informed on our announcement mailing list.
Universal Verification Methodology (UVM)-Based Stream Generator Environment for RISC-V Cores
Contributed by Google, the environment provides configurable, highly stressful instruction sequences that can verify architectural and micro-architectural corner-cases of designs.
Western Digital is planning to contribute their high performance, 9-stage, dual issue, 32-bit SweRV Core, together with a test bench, and high performance SweRV Instruction set simulator. Additional contribution will be specification and early implementations of OmniXtend cache coherence protocol.
CHIPS Alliance will create a neutral, independent entity where companies and individuals can collaborate and contribute resources to make open source CPU chip and system-on-a-chip (SoC) design more accessible to the market.
CHIPS Alliance aims to host implementation efforts around RISC-V architecture (RISC-V is only for ISAs and will not host implementations). RISC-V will help set up an ISA instruction set, but will then need open sourced chip designs; CHIPS Alliance will create that open source standard computing design. Members and participants of CHIPS Alliance will then be able to download source code and compile binaries to get Linux running and offer a fully functional CPU or SoC design with RISC-V.
Additionally, it is possible that some attractive open source hardware projects, such as accelerators for Neural Network inference workloads, or memory controllers for emerging non-volatile memories, may be outside of scope of instructions set architectures in general.
CHIPS Alliance will play an important role for the entire silicon devices ecosystem that includes application developers, device manufacturers and hardware designers across the chip, mobile, computing, consumer electronics, and Internet of Things (IOT) sectors.
The Linux Foundation is an ideal home for many open source projects. RISC-V Foundation is an organization that focuses on software-hardware interface – known as an instruction set architecture (ISA) – but does not specify actual microarchitecture implementations, that may span a broad range from IoT/microcontroller to datacenter applications. The microarchitecture implementations are exactly the scope of the CHIPS Alliance.
We expect collaboration activity to ramp up early summer 2019, focused on initial projects around RISC-V compute cores, design tools, and design verification methodologies.
While it’s early days and the forthcoming community will work together to determine what projects will be part of CHIPS Alliance, our early contributions will likely include Western Digital’s SweRV Core (including a testbench and instruction set simulator), OmniXtend cache coherence over ethernet protocol, Universal Verification Methodology for RISC-V compute elements and design tools.
We hope to bring innovation in areas such as multi RISC-V core, Linux capable based SoCs and CPUs that will open not only RISC-V based compute architecture, but will also bring open interfaces such as NVDIMM-P memory controller interfaces, accelerator interfaces for machine learning accelerator devices, and smart networking interfaces such as OmniXtend, under one umbrella project, including design and design verification.